Firestorm: TBL (four register table, 16B) measurements

Code:

  tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 3.001

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 3.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
3004	4037	30	0	0	0	0	0	1	61	3676	25	3001	3000	3000	549641	1	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3821	3000	4038	4038	4038	4038	4038
3004	4037	31	0	0	0	12	0	1	61	3676	25	3001	3000	3000	549641	1	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3821	3000	4038	4038	4038	4038	4038
3004	4037	30	0	0	0	0	0	0	103	3676	25	3000	3001	3000	549645	1	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3821	3000	4038	4038	4038	4038	4038
3004	4037	30	0	0	0	0	0	0	61	3676	25	3001	3004	3000	549641	1	4018	4037	4037	3335	22	3645	3000	3000	9000	4049	4037	1	1	1001	1000	1	0	0	73	2	16	2	2	3821	3000	4038	4038	4038	4038	4038
3004	4037	30	0	0	0	0	0	0	61	3676	25	3000	3000	3000	549641	0	4018	4049	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3821	3000	4038	4038	4038	4050	4038
3004	4037	31	0	0	1	3	0	1	61	3676	25	3004	3001	3000	549641	1	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3821	3000	4038	4050	4038	4038	4038
3004	4037	30	0	0	0	0	0	1	61	3676	25	3000	3000	3000	549641	0	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	87	73	2	16	2	2	3821	3000	4038	4038	4050	4038	4038
3004	4037	31	0	0	0	0	0	1	61	3676	25	3000	3001	3000	549641	1	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3821	3000	4038	4038	4038	4038	4038
3004	4037	30	0	0	0	0	0	0	82	3676	25	3001	3000	3000	551410	1	4030	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	27	73	2	16	2	2	3821	3000	4038	4038	4038	4038	4038
3004	4037	30	0	0	0	0	0	1	61	3676	25	3004	3000	3000	549641	0	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3821	3000	4038	4038	4038	4038	4038

Test 2: Latency 1->2

Code:

  tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	40037	300	0	0	0	0	0	0	1	0	61	39676	25	30100	100	30001	100	30000	500	5706641	1	40018	40049	40049	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	29	0	0	0	710	1	3	16	3	3	39819	0	30000	100	40038	40038	40038	40050	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39676	25	30104	100	30000	100	30000	500	5706641	1	40018	40037	40037	35947	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	29	0	0	0	710	1	3	16	3	3	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39676	25	30100	100	30000	100	30000	500	5706645	1	40030	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	27	0	0	0	710	1	3	16	3	3	39831	0	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	0	0	0	1	0	61	39676	25	30100	100	30000	100	30000	500	5706641	1	40018	40037	40037	35935	3	36257	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	3	16	3	3	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	1	0	61	39676	25	30104	100	30001	100	30000	500	5706645	1	40018	40037	40049	35935	3	36245	30100	200	30000	200	90000	40049	40049	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	3	16	3	3	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39676	25	30101	100	30000	100	30000	500	5706641	1	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40049	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	3	16	3	3	39819	0	30000	100	40038	40038	40050	40038	40050
30204	40037	300	0	0	0	0	0	0	4	0	61	39676	25	30100	100	30001	100	30000	500	5706641	1	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40049	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	3	16	3	3	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	0	0	0	1	0	61	39697	25	30104	100	30000	100	30000	500	5706641	1	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	0	710	1	3	16	3	3	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	0	0	0	1	0	61	39676	25	30104	100	30000	100	30000	500	5706645	1	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	0	6	0	710	1	3	16	3	3	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39676	25	30104	100	30000	100	30000	500	5706645	1	40018	40049	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	51	0	3	0	710	1	3	16	3	3	39819	0	30000	100	40038	40050	40038	40038	40050

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	40037	300	0	0	0	0	0	0	0	61	39682	25	30011	10	30000	10	30000	50	5706645	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	20	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	1	61	39691	25	30010	10	30001	10	30000	50	5706641	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10022	10	9	10	10	10000	10	0	0	0	1	0	3	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40050
30024	40040	300	0	0	0	0	0	0	1	61	39676	25	30010	10	30000	10	30000	50	5706643	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	2	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	309	0	0	0	0	0	0	1	61	39676	25	30011	10	30000	10	30000	50	5706645	1	40018	40037	40049	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	2	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	1	61	39676	25	30010	10	30001	10	30000	50	5706641	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	299	0	0	0	0	0	0	0	82	39676	25	30011	10	30001	10	30000	50	5706641	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40262
30024	40037	300	0	0	0	0	0	0	1	61	39676	25	30010	10	30004	10	30000	50	5706641	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40049	300	0	0	0	0	0	0	1	61	39676	25	30014	10	30001	10	30000	50	5706641	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40041
30024	40037	299	0	0	0	0	0	0	0	61	39682	25	30014	10	30000	10	30000	50	5706645	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39818	0	30000	10	40050	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	1	61	39679	25	30011	10	30000	10	30000	50	5706645	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40050

Test 3: Latency 1->3

Code:

  tbl v1.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	40037	300	0	0	0	0	0	0	0	0	61	39676	25	30100	100	30000	100	30000	500	5706641	1	40018	40037	40037	35942	0	6	36241	30100	200	30008	200	90024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	0	0	16	0	0	0	39840	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39676	25	30209	100	30001	100	30000	500	5706641	1	40018	40037	40037	35935	0	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	0	2	16	0	3	2	39819	0	30000	100	40038	40038	40050	40038	40038
30204	40037	300	0	0	0	0	3	0	0	0	61	39676	25	30101	100	30001	100	30000	500	5706645	1	40018	40037	40037	35935	0	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	2	2	1	0	2	27943	0	0	0	0	947	1	0	4	142	0	2	2	40169	17	30000	100	40792	40782	40627	40836	40460
30204	40828	306	0	1	14	14	1848	1316	2	0	103	39676	122	30471	133	30526	126	31792	626	5708753	1	40318	40402	40462	35891	0	58	36383	32143	218	31421	215	94995	40526	40411	9	1	10201	100	99	100	100	10000	100	0	0	0	0	2	0	2	0	0	0	710	1	0	8	163	0	5	4	40280	18	30000	100	40623	40896	40815	40796	40840
30204	40819	305	0	0	10	16	1200	1232	12	0	7426	39285	236	31434	131	31206	136	33136	670	5709343	1	40684	40820	40616	35928	0	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	3	0	0	0	0	710	1	0	2	97	0	2	3	39819	17	30000	100	40050	40465	40038	40145	40251
30204	40466	299	1	0	14	2	1860	1144	19	4	4022	39327	339	31440	131	31133	100	30000	500	5706641	1	40612	40285	40810	35859	0	82	36360	32141	220	30938	204	93555	40251	40307	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	0	2	16	0	2	2	39819	0	30000	100	40038	40038	40038	40097	40038
30204	40037	300	0	0	0	0	0	0	1	0	61	39676	25	30100	100	30000	100	30000	500	5706641	1	40018	40037	40037	35935	0	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	712	1	0	2	16	0	2	2	39819	0	30000	100	40038	40038	40038	40096	40038
30204	40037	300	0	0	0	0	0	0	0	0	296	39676	25	30101	100	30000	100	30000	500	5706641	1	40018	40037	40037	35935	0	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	0	2	16	0	2	2	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	0	0	0	1	0	61	39676	44	30101	100	30000	100	30000	500	5706645	0	40018	40037	40037	35935	0	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	0	2	16	0	3	2	39819	0	30000	100	40050	40038	40038	40038	40038
30204	40049	300	0	0	0	0	0	0	1	1	61	39676	25	30100	100	30000	100	30000	500	5708410	0	40018	40037	40037	35935	0	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	0	2	16	0	2	2	39819	0	30000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	40037	310	0	0	1	61	39676	25	30011	10	30000	10	30000	50	5706645	0	1	40018	0	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	2	0	0	640	3	16	3	3	39818	30000	10	40050	40038	40038	40050	40038
30024	40037	300	0	0	0	61	39676	25	30011	10	30000	10	30000	50	5706645	0	1	40018	0	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39818	30000	10	40038	40038	40038	40038	40038
30024	40037	300	1	0	1	726	39676	25	30010	10	30000	10	30000	50	5706645	0	1	40018	0	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39818	30000	10	40050	40050	40038	40209	40038
30024	40037	300	0	0	1	61	39676	25	30010	10	30001	10	30000	50	5706641	0	1	40018	0	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39818	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	3	1	61	39676	25	30010	10	30000	11	30000	50	5706645	0	1	40018	0	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	640	3	16	3	3	39818	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	61	39676	25	30010	10	30001	10	30000	50	5706641	0	1	40018	0	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39830	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	497	39676	25	30011	10	30000	10	30000	50	5706643	0	1	40018	0	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39818	30000	10	40038	40038	40086	40038	40038
30024	40037	299	0	0	0	441	39676	25	30011	10	30001	10	30000	50	5706645	0	1	40018	0	40037	40040	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39818	30000	10	40038	40038	40050	40038	40038
30024	40037	300	0	0	1	61	39676	25	30014	10	30000	10	30000	50	5706645	0	1	40018	0	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	662	3	16	3	3	39818	30000	10	40038	40038	40038	40038	40038
30024	40037	299	0	0	1	61	39676	25	30011	10	30001	10	30000	50	5706641	0	0	40018	0	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39818	30000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->4

Code:

  tbl v2.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	40037	300	0	0	0	61	39703	25	30100	100	30001	100	30000	500	5706624	0	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	39822	30000	100	40038	40038	40041	40062	40038
30204	40037	300	0	0	0	61	39690	25	30101	100	30000	100	30000	500	5706623	0	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40037	40040	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39819	30000	100	40038	40038	40041	40062	40038
30204	40040	300	0	1	0	61	39687	25	30108	100	30000	100	30000	500	5706623	0	40021	40037	40037	35937	3	36245	30100	200	30000	200	90000	40037	40055	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39819	30000	100	40038	40041	40038	40041	40038
30204	40037	300	0	0	0	61	39703	25	30100	100	30000	100	30000	500	5706624	1	40021	40037	40040	35934	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39822	30000	100	40038	40038	40038	40038	40038
30204	40061	300	0	0	0	156	39687	25	30100	100	30000	100	30000	500	5706623	1	40018	40037	40040	35958	3	36245	30100	200	30000	200	90000	40061	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	39819	30000	100	40038	40038	40041	40041	40038
30204	40037	299	0	0	1	61	39687	25	30101	100	30001	100	30000	500	5706624	0	40018	40040	40037	35934	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39819	30000	100	40038	40038	40041	40038	40038
30204	40037	300	0	0	0	61	39687	25	30101	100	30001	100	30000	500	5706623	1	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39819	30000	100	40038	40041	40062	40038	40038
30204	40037	300	0	1	0	61	39687	25	30101	100	30008	100	30000	500	5707057	0	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40037	40040	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39819	30000	100	40038	40038	40038	40041	40038
30204	40037	300	0	1	0	61	39687	25	30101	100	30001	100	30000	500	5706624	0	40018	40040	40037	35934	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39822	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	8	0	61	39687	25	30101	100	30001	100	30000	500	5706624	0	40018	40037	40061	35934	3	36245	30100	200	30000	200	90000	40061	40040	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39819	30000	100	40038	40062	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	40037	300	0	0	0	61	39697	25	30016	10	30000	10	30000	50	5706624	0	40018	40061	40037	35980	0	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39817	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	61	39703	25	30018	10	30008	10	30000	50	5706624	1	40018	40037	40037	35956	0	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	2	39817	30000	10	40038	40038	40038	40038	40056
30024	40037	299	0	0	6	61	39687	25	30010	10	30000	10	30000	50	5710400	0	40042	40061	40037	35956	0	3	36291	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	2	2	39817	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	8	61	39687	25	30011	10	30000	10	30000	50	5706624	0	40065	40037	40037	35956	0	3	36267	30010	20	30000	20	90000	40061	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	2	3	39817	30000	10	40038	40038	40038	40038	40056
30024	40055	300	0	0	0	61	39687	25	30010	10	30000	10	30000	50	5706624	0	40018	40037	40037	35956	0	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	3	39817	30000	10	40038	40056	40038	40062	40038
30024	40037	300	0	0	0	61	39687	25	30010	10	30001	10	30000	50	5706624	0	40018	40037	40037	35956	0	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39817	30000	10	40038	40038	40062	40056	40062
30024	40037	300	0	0	8	61	39687	25	30010	10	30000	10	30000	50	5710400	0	40018	40037	40037	35956	0	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39817	30000	10	40038	40062	40038	40062	40041
30024	40061	300	0	0	0	61	39687	25	30018	10	30000	10	30000	50	5710400	0	40018	40061	40061	35980	0	3	36291	30010	20	30000	20	90000	40061	40037	1	1	10021	10	9	10	10	10000	10	0	3	0	1	640	3	16	3	3	39817	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	61	39687	25	30010	10	30000	10	30000	50	5706624	0	40018	40037	40037	35956	0	3	36267	30010	20	30000	20	90000	40055	40061	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39817	30000	10	40038	40038	40038	40038	40038
30024	40040	300	0	0	8	61	39687	25	30010	10	30008	10	30000	50	5706624	0	40042	40061	40061	35956	0	3	36291	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39817	30000	10	40041	40038	40038	40038	40038

Test 5: Latency 1->5

Code:

  tbl v3.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	18	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	40037	300	0	0	285	0	0	61	39690	25	30101	100	30001	100	30000	500	5706624	40021	40040	40037	35958	3	36245	30100	200	30000	200	90000	40061	40040	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	3	16	3	3	39819	30000	100	40038	40041	40038	40038	40038
30204	40037	300	0	0	0	1	0	61	39690	25	30100	100	30000	100	30000	500	5706624	40018	40037	40040	35934	3	36245	30100	200	30000	200	90000	40037	40061	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	3	16	3	3	39819	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	6	0	0	61	39687	25	30100	100	30008	100	30000	500	5706623	40018	40037	40037	35937	3	36245	30100	200	30000	200	90000	40037	40040	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	3	16	3	3	39819	30000	100	40038	40038	40038	40038	40041
30204	40037	300	0	1	54	0	0	61	39687	25	30101	100	30001	100	30000	500	5707057	40018	40037	40037	35934	3	36248	30100	200	30000	200	90000	40040	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	3	16	3	3	39819	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	61	39690	25	30108	100	30000	100	30000	500	5707057	40018	40061	40037	35934	3	36248	30100	200	30000	200	90000	40037	40040	1	1	10201	100	99	100	100	10000	100	0	0	0	712	1	3	16	3	3	39819	30000	100	40062	40038	40038	40038	40038
30204	40037	300	0	0	0	1	0	61	39687	25	30106	100	30001	100	30000	500	5706623	40018	40037	40037	35934	3	36248	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	3	3	39819	30000	100	40038	40038	40041	40038	40038
30204	40037	300	0	0	0	1	0	61	39687	25	30100	100	30000	100	30000	500	5706624	40018	40037	40089	35923	11	36291	30100	200	30000	200	90000	40040	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	4	3	39819	30000	100	40041	40038	40038	40062	40038
30204	40040	300	0	0	0	0	0	61	39690	25	30100	100	30000	100	30000	500	5706624	40018	40037	40037	35937	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	712	1	3	16	3	3	39819	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	1	0	82	39703	25	30101	100	30000	100	30000	500	5706623	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40037	40040	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	3	3	39819	30000	100	40038	40038	40038	40038	40041
30204	40040	299	0	0	51	1	0	61	39687	25	30100	100	30001	100	30000	500	5706624	40042	40040	40037	35934	3	36245	30100	200	30000	200	90753	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	3	3	39822	30000	100	40038	40038	40062	40041	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	40037	300	0	48	0	536	39687	25	30010	10	30000	10	30000	50	5709536	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40055	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39820	0	30000	10	40038	40038	40038	40062	40038
30024	40037	300	0	30	8	61	39687	25	30011	10	30000	10	30000	50	5707057	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39817	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	354	0	61	39703	25	30010	10	30000	10	30000	50	5706624	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39817	0	30000	10	40062	40038	40038	40038	40038
30024	40037	300	0	42	0	61	39687	25	30010	10	30000	10	30000	50	5706624	40018	40037	40037	35956	3	36270	30010	20	30000	20	90000	40040	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	3	2	39817	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	9	8	61	39687	25	30010	10	30000	10	30000	50	5710400	40018	40037	40037	35980	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39817	0	30000	10	40041	40038	40038	40038	40038
30024	40037	299	0	96	8	61	39687	25	30010	10	30000	10	30000	50	5710400	40042	40061	40037	35956	3	36267	30010	20	30000	20	90000	40037	40084	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39817	0	30000	10	40038	40038	40038	40056	40038
30024	40037	300	0	24	0	232	39687	25	30010	10	30000	10	30000	50	5706624	40018	40037	40061	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	3	39817	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	24	1	61	39687	25	30010	10	30000	10	30000	50	5706624	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39835	0	30000	10	40041	40038	40038	40056	40038
30024	40037	300	0	51	1	61	39690	25	30011	10	30001	10	30000	50	5707057	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39817	0	30000	10	40038	40038	40038	40038	40062
30024	40037	300	0	27	0	61	39690	25	30010	10	30000	10	30000	50	5706624	40018	40037	40037	35959	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39817	0	30000	10	40038	40056	40062	40038	40038

Test 6: Latency 1->6

Code:

  tbl v4.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch indir (93)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	40037	300	0	0	0	0	0	69	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	0	0	0	710	0	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	30	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	40065	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	40018	40037	40037	36025	3	36245	30100	200	30182	200	90000	40037	40037	1	1	10202	100	99	0	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	17	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	726	39779	25	30100	100	30000	100	30000	500	5714347	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	0	0	0	0	0	3002	39779	25	30100	100	30000	100	30000	500	5714347	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40087
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40084	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	0	0	0	731	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	3	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	1	61	39779	25	30100	100	30000	100	30000	500	5714347	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	40037	300	0	0	0	51	0	61	39779	25	30010	10	30000	10	30000	50	5714347	1	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	27	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40065	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	3	3	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	1	1	36	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	3	0	61	39779	25	30010	10	30000	10	30000	50	5714347	1	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	6	0	61	39779	25	30010	10	30000	10	30000	50	5714347	1	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	7	0	0	0	0	640	2	16	3	3	39888	0	30000	10	40038	40038	40038	40038	40083
30024	40037	300	0	0	0	6	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	6	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	1	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	39888	0	30000	10	40038	40038	40038	40038	40038

Test 7: throughput

Count: 8

Code:

  tbl v0.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v1.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v2.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v3.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v4.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v5.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v6.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v7.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12
  movi v12.16b, 13

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240204	60042	450	0	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5116	16	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	450	0	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5116	16	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	449	0	0	33	25	240106	100	240006	100	240020	500	2280103	1	60023	60042	60042	29977	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5116	16	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	450	0	0	33	25	240106	100	240006	100	240020	500	2280103	1	60023	60042	60042	29977	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5116	16	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	449	0	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5116	16	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	449	0	0	33	25	240106	100	240006	100	240020	500	2280103	1	60023	60042	60042	29977	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5116	16	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	451	0	0	33	25	240106	100	240006	100	240020	500	2280103	1	60023	60042	60042	29977	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5116	16	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	450	0	0	698	25	240106	100	240006	100	240020	500	2280103	1	60023	60042	60042	29977	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5116	16	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	450	0	0	33	25	240106	100	240006	100	240020	500	2280103	1	60023	60042	60042	29977	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5116	16	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	449	0	0	33	25	240106	100	240006	100	240020	500	2280103	1	60023	60042	60042	29977	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5116	16	60039	0	240000	100	60043	60043	60043	60043	60043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240024	60053	450	0	0	0	9	518	25	240010	10	240000	10	240000	50	2279971	60023	0	60042	60042	29996	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	4	16	4	3	60039	240000	10	60255	60043	60043	60094	60043
240024	60042	450	0	0	0	0	43	25	240010	10	240000	10	240000	50	2279971	60144	0	60042	60042	29996	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	3	0	0	0	5020	4	16	3	3	60039	240000	10	60043	60043	60043	60043	60043
240024	60042	449	0	0	0	0	43	25	240010	10	240000	10	240434	50	2279971	60023	0	60042	60042	29996	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	3	0	5073	5	16	4	3	60039	240000	10	60043	60043	60043	60043	60043
240024	60042	450	0	1	0	12	43	25	240010	10	240000	10	240000	50	2279971	60023	0	60042	60042	29996	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	4	0	0	1	5020	3	16	3	3	60039	240000	10	60043	60043	60043	60250	60043
240024	60042	450	0	0	0	0	708	25	240010	10	240000	10	240000	50	2279971	60023	0	60042	60042	29996	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	3	16	3	3	60039	240000	10	60043	60043	60043	60043	60043
240024	60042	450	0	0	0	0	43	25	240010	10	240000	10	240000	50	2279971	60023	0	60042	60042	29996	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	5	16	5	3	60039	240000	10	60043	60043	60043	60043	60043
240024	60042	449	0	0	0	0	43	25	240010	10	240000	10	240000	50	2279971	60023	0	60042	60042	29996	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	3	16	3	3	60039	240000	10	60043	60043	60043	60043	60043
240024	60042	449	0	0	0	0	43	25	240010	10	240000	10	240000	50	2279971	60023	0	60042	60042	29996	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	10	4	0	0	5020	3	16	3	4	60039	240000	10	60043	60043	60043	60043	60043
240024	60042	450	0	0	0	0	87	25	240010	10	240000	10	240000	50	2279971	60023	0	60042	60042	29996	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	5	16	3	3	60039	240000	10	60043	60043	60043	60043	60043
240024	60042	449	0	0	0	54	43	25	240010	10	240000	10	240000	50	2279971	60789	0	60915	60984	30228	97	30614	242549	20	242113	20	726306	61089	61141	22	1	80021	10	9	10	10	80000	10	2	4	1	0	0	0	0	5020	5	16	5	5	60039	240000	10	60043	60043	60043	60043	60043

TBL (four register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->6

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations