Firestorm: TBL (four register table, 8B) measurements

Code:

  tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 3.001

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 3.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	37	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
3004	4037	30	0	0	0	0	61	3676	25	3000	3000	3000	551410	0	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3821	3000	4038	4038	4038	4038	4038
3004	4037	30	0	0	0	4	105	3676	25	3000	3001	3000	549641	0	4018	4037	4037	3335	3	3645	3000	3000	9000	4049	4037	1	1	1001	1000	0	0	73	1	16	1	1	3821	3000	4038	4038	4038	4038	4038
3004	4037	30	0	0	0	0	105	3689	25	3000	3000	3000	549645	1	4018	4037	4037	3335	3	3645	3000	3000	9000	4049	4037	1	1	1001	1000	1	0	73	1	16	1	1	3821	3000	4038	4038	4038	4050	4038
3004	4037	30	0	0	0	0	61	3676	25	3000	3000	3000	549641	0	4030	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	2	0	73	1	16	1	1	3821	3000	4038	4038	4038	4038	4038
3004	4037	30	0	0	0	1	61	3676	25	3001	3001	3000	549645	1	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3833	3000	4038	4050	4038	4038	4038
3004	4037	30	0	0	0	0	82	3676	25	3000	3001	3000	549641	1	4018	4049	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3821	3000	4038	4038	4038	4038	4038
3004	4037	30	0	0	0	1	61	3676	25	3000	3001	3000	549645	0	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3821	3000	4038	4038	4038	4038	4038
3004	4037	30	0	0	0	1	61	3676	25	3000	3001	3000	549645	1	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3821	3000	4038	4038	4038	4038	4038
3004	4037	32	0	0	0	1	61	3676	25	3000	3004	3000	549641	1	4018	4037	4037	3335	3	3645	3000	3000	9000	4049	4037	1	1	1001	1000	0	0	73	1	16	1	1	3821	3000	4050	4038	4038	4050	4050
3004	4037	30	0	0	0	1	61	3676	25	3000	3001	3000	549641	0	4018	4037	4037	3335	3	3645	3000	3000	9000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3821	3000	4038	4038	4038	4038	4038

Test 2: Latency 1->2

Code:

  tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	40037	300	0	0	0	4	0	61	39676	25	30101	100	30001	100	30000	500	5708410	0	40018	40037	40037	35942	6	36240	30100	200	30008	200	90024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39819	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	61	39676	25	30100	100	30001	100	30000	500	5706645	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	1	6	710	1	2	16	3	2	39819	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	61	39676	25	30100	100	30001	102	30000	500	5708410	1	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	39819	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	4	0	61	39691	25	30101	100	30001	100	30000	500	5706645	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	3	710	1	2	16	2	2	39831	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	61	39691	25	30100	100	30001	100	30000	500	5706645	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	2	39819	30000	100	40038	40038	40038	40084	40038
30204	40037	300	0	0	0	4	0	61	39676	25	30100	100	30000	100	30000	500	5706645	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	39819	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	1	0	92	39676	25	30101	100	30000	100	30000	500	5706641	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40049	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	39819	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	1	0	61	39676	25	30101	100	30001	100	30000	500	5706645	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	39831	30000	100	40050	40038	40038	40038	40038
30204	40037	299	0	0	0	4	0	223	39676	25	30197	100	30000	100	30000	500	5706645	1	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	39819	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	1	0	747	39676	25	30100	100	30001	100	30000	500	5706641	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39819	30000	100	40038	40050	40050	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	40037	300	0	0	0	0	0	1	726	39676	25	30010	10	30001	10	30000	50	5706641	0	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	3	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	299	0	0	0	0	0	0	61	39676	25	30010	10	30000	10	30000	50	5706645	0	40018	40037	40037	35973	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	4	61	39676	25	30011	10	30001	10	30000	50	5706643	0	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	1	103	39676	25	30011	10	30001	10	30000	50	5706645	0	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	3	39830	0	30000	10	40038	40038	40038	40038	40038
30024	40040	300	0	0	0	0	0	1	61	39682	25	30010	10	30000	10	30000	50	5706645	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	1	251	39676	25	30011	10	30001	10	30000	50	5706643	0	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	3	39818	0	30000	10	40038	40038	40038	40038	40041
30024	40037	300	0	0	0	0	0	1	82	39676	144	30358	10	30174	10	30000	50	5706643	0	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	4	191	39676	25	30011	10	30001	10	30000	50	5706641	0	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	1	147	39676	25	30010	10	30001	10	30000	50	5706641	0	40018	40037	40037	35957	26	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	1	61	39676	25	30010	10	30001	10	30000	50	5706645	0	40030	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39818	0	30000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->3

Code:

  tbl v1.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	40037	300	1	0	0	0	0	15	0	0	0	407	39676	25	30100	100	30001	100	30000	500	5706641	0	0	40018	40037	40037	35935	3	36257	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	0	0	3	16	2	2	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	1	0	593	39676	25	30100	100	30000	100	30000	500	5706645	0	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	0	0	2	16	2	2	39819	0	30000	100	40038	40038	40038	40038	40050
30204	40037	299	0	0	0	0	0	0	0	0	1	61	39676	25	30101	100	30001	100	30000	500	5706641	0	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	0	0	2	16	3	2	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	0	0	0	0	1	0	61	39676	25	30101	100	30001	100	30000	500	5706641	0	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	0	0	2	16	2	2	39819	0	30000	100	40050	40050	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	0	1049	39676	25	30100	100	30001	100	30000	500	5706641	0	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	0	0	2	16	2	2	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	0	0	0	0	4	1	61	39676	25	30101	100	30086	100	30000	500	5706641	0	0	40018	40141	40037	35935	21	36245	30324	200	30000	200	90000	40037	40049	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	0	0	2	16	3	2	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	1	0	61	39676	25	30101	100	30001	100	30000	500	5706645	0	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	712	1	0	0	2	16	2	2	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	1	0	61	39676	25	30101	100	30000	100	30000	500	5706641	0	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	0	0	0	710	1	0	0	2	16	3	2	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	1	0	61	39676	25	30100	100	30000	100	30000	500	5706645	0	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	0	0	2	16	2	2	39819	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	1	0	66	39676	25	30101	100	30000	100	30000	500	5706641	0	0	40018	40037	40037	35935	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	2	0	0	0	0	0	710	1	0	0	2	16	2	2	39819	0	30000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	40037	299	0	0	0	0	1	0	1259	39676	25	30010	10	30001	10	30000	50	5706641	0	40030	40049	40049	35957	3	36267	30010	20	30252	20	90000	40037	40049	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	3	2	39818	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	1	0	66	39676	25	30011	10	30004	10	30000	50	5708410	1	40018	40049	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	3	3	39818	30000	10	40038	40038	40050	40050	40038
30024	40037	300	0	0	0	0	0	0	61	39676	25	30010	10	30000	10	30000	50	5708410	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40049	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	3	3	39818	30000	10	40038	40038	40038	40050	40038
30024	40037	299	0	0	0	0	0	0	726	39676	25	30011	10	30000	10	30000	50	5706643	0	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	4	3	39818	30000	10	40038	40038	40038	40038	40050
30024	40037	299	0	0	0	0	0	0	61	39676	25	30011	10	30001	10	30000	50	5706641	1	40018	40037	40037	35957	3	36267	30231	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	3	3	39818	30000	10	40038	40038	40050	40050	40038
30024	40037	300	0	0	0	0	0	0	61	39676	25	30011	10	30001	10	30000	50	5706645	0	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	3	3	39818	30000	10	40050	40038	40038	40038	40038
30024	40037	299	0	0	0	0	0	0	61	39676	25	30011	10	30000	10	30000	50	5706641	1	40018	40064	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	3	39818	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	4	0	61	39676	25	30010	10	30001	10	30000	50	5706641	1	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39818	30000	10	40038	40038	40038	40038	40038
30024	40049	300	0	0	0	0	0	0	726	39682	25	30010	10	30000	10	30000	50	5706641	0	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	4	3	39818	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	61	39676	25	30011	10	30001	10	30000	50	5706645	0	40018	40037	40037	35957	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	2	3	39830	30000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->4

Code:

  tbl v2.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	40037	299	0	0	1	0	0	0	0	1072	39697	25	30101	100	30094	100	30000	566	5706624	1	40018	40037	40040	35952	3	36245	30100	200	30000	200	90000	40040	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	2	0	924	0	3	142	5	3	40422	23	30000	100	40892	40634	40928	40734	40939
30204	40849	306	1	15	15	1980	1320	20	0	5857	39386	169	31115	126	30995	135	32700	649	5714267	1	40534	40634	40411	35904	104	36509	32837	217	33093	222	99297	40359	40676	12	1	10201	100	99	100	100	10000	100	0	2	1	2	27820	4	0	932	0	2	163	5	3	40314	15	30000	100	40876	40931	40921	40951	40038
30204	40037	300	0	0	0	15	0	0	0	124	39690	25	30101	100	30000	100	30000	500	5706623	1	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	39819	0	30000	100	40038	40041	40038	40041	40038
30204	40037	300	0	0	0	0	0	0	0	726	39687	25	30101	100	30001	100	30000	500	5706623	1	40018	40037	40037	35934	25	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	2	0	0	0	0	0	0	710	1	2	16	3	2	39837	0	30000	100	40041	40038	40038	40062	40038
30204	40037	300	0	0	0	0	0	1	0	61	39690	25	30101	100	30000	100	30000	500	5706624	1	40018	40037	40037	35934	3	36269	30100	200	30000	200	90000	40037	40040	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	3	2	39822	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	61	39687	25	30100	100	30008	100	30000	500	5707057	1	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40061	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2010	0	0	710	1	2	16	3	2	39819	0	30000	100	40038	40038	40038	40038	40041
30204	40037	299	0	0	0	78	0	1	0	61	39687	25	30101	100	30001	100	30000	500	5706624	0	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40037	40061	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	3	2	39819	0	30000	100	40038	40038	40062	40038	40041
30204	40040	300	0	0	0	0	0	1	0	1661	39687	25	30100	100	30000	100	30000	500	5706624	0	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40040	40061	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	26	2	2	39819	0	30000	100	40062	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	8	0	61	39690	25	30100	100	30000	100	30000	500	5710400	1	40042	40037	40037	35934	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	3	2	39822	0	30000	100	40041	40062	40038	40038	40041
30204	40037	300	0	0	0	0	0	1	0	61	39687	25	30101	100	30001	100	30000	500	5706624	1	40018	40040	40061	35934	3	36269	30100	200	30000	200	90000	40061	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	3	2	39819	2	30000	100	40062	40041	40038	40062	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	40037	300	0	0	0	0	0	0	0	1	1255	39687	25	30010	10	30000	10	30000	50	5706624	1	40018	40049	40049	35968	3	36267	30010	20	30000	20	90000	40061	40049	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	39820	30000	10	40038	40038	40038	40038	40062
30024	40055	300	0	0	0	0	0	0	0	2	1865	39703	25	30010	10	30000	10	30000	50	5710400	0	40030	40037	40037	35956	3	36267	30010	20	30000	20	90000	40055	40037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	39835	30000	10	40038	40038	40062	40056	40038
30024	40037	300	0	0	0	0	0	0	0	0	1873	39694	25	30010	10	30000	10	30000	50	5706624	0	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	39817	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	0	0	1868	39687	25	30011	10	30000	10	30000	50	5706624	0	40042	40061	40055	35974	3	36291	30010	20	30000	20	90000	40055	40037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	39817	30000	10	40038	40038	40050	40038	40038
30024	40037	300	0	0	0	0	0	0	0	8	1294	39690	25	30011	10	30000	10	30000	50	5710400	0	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40040	40037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	39817	30000	10	40056	40050	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	0	0	526	39687	25	30014	10	30026	10	30000	50	5710400	0	40042	40061	40037	35956	3	36267	30010	20	30000	20	90000	40037	40061	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	39841	30000	10	40062	40041	40038	40038	40083
30024	40037	300	0	0	0	0	0	0	0	6	1853	39687	25	30010	10	30000	10	30000	50	5706624	0	40018	40037	40037	35968	3	36270	30234	20	30000	20	90000	40052	40037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	39817	30000	10	40038	40041	40041	40038	40038
30024	40061	300	0	0	0	0	0	0	0	8	1802	39687	25	30016	10	30006	10	30000	50	5706624	0	40018	40037	40055	35974	3	36285	30010	20	30000	20	90000	40055	40037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	39817	30000	10	40050	40038	40038	40050	40038
30024	40037	300	0	0	0	0	0	0	0	8	1861	39687	25	30010	10	30035	10	30000	50	5706624	0	40042	40037	40037	35974	3	36267	30010	20	30000	20	90000	40055	40037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	39817	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	0	0	1333	39687	25	30010	10	30000	10	30000	50	5706624	1	40021	40040	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	39817	30000	10	40074	40038	40038	40041	40041

Test 5: Latency 1->5

Code:

  tbl v3.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	40037	300	0	24	6	0	61	39687	25	30100	100	30000	100	30450	533	5707612	0	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40115	40090	1	1	10201	100	99	100	100	10000	100	0	0	710	0	4	16	2	2	39819	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	1	1	61	39687	25	30100	100	30000	100	30000	500	5706624	0	40021	40037	40037	35934	3	36245	30100	200	30000	200	90000	40037	40040	1	1	10201	100	99	100	100	10000	100	1	0	710	1	2	16	2	2	39819	30000	100	40038	40038	40062	40038	40038
30204	40037	300	0	0	1	0	61	39687	25	30101	100	30001	100	30000	500	5706624	0	40021	40040	40061	35937	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39822	30000	100	40038	40041	40038	40038	40038
30204	40037	300	0	0	1	0	61	39687	25	30100	100	30001	100	30000	500	5706623	0	40018	40037	40037	35934	3	36245	30100	200	30000	200	90000	40037	40040	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	2	39819	30000	100	40062	40038	40038	40038	40038
30204	40037	300	0	0	1	0	61	39687	25	30101	100	30000	100	30000	500	5706623	0	40042	40061	40037	35937	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	39819	30000	100	40038	40038	40041	40038	40038
30204	40037	300	0	0	0	0	251	39687	25	30101	100	30000	100	30000	500	5706624	0	40042	40040	40037	35958	3	36248	30100	200	30000	200	90000	40037	40249	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	39843	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	1	0	61	39690	25	30100	100	30000	100	30000	500	5706623	0	40018	40061	40037	35934	3	36245	30100	200	30000	200	90000	40037	40040	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	2	2	39819	30000	100	40038	40038	40056	40038	40038
30204	40037	300	0	0	1	0	61	39687	25	30101	100	30001	100	30000	500	5707057	0	40021	40037	40040	35937	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39819	30000	100	40041	40038	40038	40038	40038
30204	40037	299	0	0	1	0	61	39687	25	30108	100	30001	100	30000	500	5707057	0	40021	40040	40061	35934	3	36245	30100	200	30000	200	90000	40037	40040	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	2	2	39819	30000	100	40062	40038	40038	40041	40038
30204	40037	300	0	0	0	0	61	39687	25	30101	100	30000	100	30000	500	5706624	0	40042	40040	40037	35958	3	36248	30100	200	30000	200	90000	40040	40037	1	1	10201	100	99	100	100	10000	100	2	0	710	1	2	16	2	2	39819	30000	100	40041	40038	40041	40038	40083

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	40037	299	0	0	0	0	0	0	0	1	61	39690	25	30010	10	30000	10	30000	50	5706624	0	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	5	16	3	3	39817	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	0	0	943	39687	25	30011	10	30000	10	30000	50	5706624	0	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	39835	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	0	1	61	39687	25	30010	10	30000	10	30000	50	5706624	0	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40055	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	4	3	39817	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	0	0	61	39687	25	30010	10	30000	10	30000	50	5706624	0	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	39820	0	30000	10	40038	40038	40038	40038	40038
30024	40037	299	0	0	0	0	0	0	0	0	61	39687	25	30010	10	30001	10	30000	50	5706624	1	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40037	40040	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	39817	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	0	0	631	39687	25	30010	10	30000	10	30000	50	5706624	0	40018	40037	40055	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	39817	0	30000	10	40038	40041	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	0	0	61	39687	25	30011	10	30000	10	30000	50	5706623	1	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	39817	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	0	0	61	39687	25	30010	10	30000	10	30000	50	5706623	1	40018	40061	40037	35956	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	39817	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	0	0	0	0	61	39687	25	30010	10	30000	10	30000	50	5706624	0	40018	40037	40037	35956	3	36267	30010	20	30000	20	90000	40090	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	640	3	16	4	4	39817	0	30000	10	40038	40038	40038	40090	40038
30024	40247	300	0	0	0	0	0	0	0	1	61	39687	25	30010	10	30000	10	30000	50	5706623	0	40018	40089	40037	35952	12	36282	30010	20	30235	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	39817	0	30000	10	40038	40038	40038	40038	40038

Test 6: Latency 1->6

Code:

  tbl v4.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	40037	299	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	0	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	712	0	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	0	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	299	0	0	0	0	0	6	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	0	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	0	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	0	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	0	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30018	100	30000	500	5714347	0	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	0	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	0	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038
30204	40037	300	0	0	0	0	0	0	0	0	61	39779	25	30100	100	30000	100	30000	500	5714347	1	40018	40037	40037	36025	3	36245	30100	200	30000	200	90000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	141	0	710	1	2	16	2	2	39887	0	30000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	40037	300	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	1	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	61	39753	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90540	40037	40037	1	1	10021	10	9	10	10	10000	10	0	12	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	21	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	103	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	300	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	299	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40037	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038
30024	40037	299	0	0	0	0	61	39779	25	30010	10	30000	10	30000	50	5714347	0	40018	40084	40037	36047	3	36267	30010	20	30000	20	90000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39888	0	30000	10	40038	40038	40038	40038	40038

Test 7: throughput

Count: 8

Code:

  tbl v0.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v1.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v2.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v3.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v4.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v5.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v6.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v7.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12
  movi v12.16b, 13

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240204	60042	450	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	0	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	6	1	1	1	5116	0	16	0	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	449	0	33	26	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	0	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5116	0	16	0	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	449	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	0	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5116	0	16	0	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	450	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	0	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	8	0	1	1	1	5116	0	16	0	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	450	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	0	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5116	0	16	0	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	450	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	0	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5116	0	16	0	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	450	0	698	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	0	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5129	0	16	0	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	449	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	0	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5116	0	16	0	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	449	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	0	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5116	0	16	0	60039	0	240000	100	60043	60043	60043	60043	60043
240204	60042	451	0	33	25	240106	100	240006	100	240020	500	2280103	0	60023	60042	60042	29977	0	6	29993	240120	200	240032	200	720096	60042	60042	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5116	0	16	0	60039	0	240000	100	60043	60043	60043	60043	60043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240024	60042	449	1	0	0	0	0	0	0	12	0	0	43	0	25	240010	10	240000	10	240000	50	2279971	0	60023	60042	60042	29996	0	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	6	16	6	6	60039	0	240000	10	60043	60043	60043	60043	60043
240024	60042	449	0	0	0	0	0	0	0	0	0	0	233	0	25	240010	10	240000	10	240000	50	2279971	0	60023	60042	60042	29996	0	3	38118	240010	20	240000	20	720000	60200	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	3	0	0	5020	7	16	7	5	60039	0	240000	10	60043	60043	60043	60043	60043
240024	60042	450	0	0	0	0	0	0	0	0	0	0	85	0	25	240010	10	240000	10	240000	50	2279971	0	60023	60042	60042	29996	0	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	6	16	7	6	60039	0	240000	10	60043	60043	60043	60043	60043
240024	60042	450	0	0	0	0	0	0	0	0	0	0	705	0	25	240010	10	240000	10	240000	50	2279971	0	60023	60042	60042	29996	0	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	6	16	6	5	60039	0	240000	10	60043	60043	60043	60043	60043
240024	60042	449	0	0	0	0	0	0	0	0	0	0	750	0	25	240010	10	240000	10	240000	50	2279971	0	60023	60042	60042	29996	0	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	1	0	12	0	0	5020	6	16	5	7	60039	0	240000	10	60043	60043	60043	60094	60043
240024	60042	450	0	0	0	0	0	0	0	0	0	0	43	0	25	240010	10	240000	10	240000	50	2283888	0	60023	60042	60042	29996	0	3	44961	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	3	0	0	5020	7	16	6	5	60039	0	240000	10	60043	60043	60043	60043	60043
240024	60042	450	0	0	0	0	0	0	0	0	0	0	61	0	25	240010	10	240000	10	240000	50	2279971	0	60023	60042	60042	29996	0	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	6	16	6	6	60039	0	240000	10	60043	60043	60043	60043	60043
240024	60042	450	0	0	0	0	0	0	0	0	0	0	43	0	25	240010	10	240000	10	240000	50	2282873	0	60023	60042	60042	29996	0	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	5	16	5	6	60039	0	240000	10	60043	60043	60043	60043	60043
240024	60042	450	0	0	0	0	0	0	0	0	0	0	43	0	25	240010	10	240000	10	240000	50	2279971	0	60023	60042	60042	29996	0	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	3	0	0	5020	6	16	6	6	60039	0	240000	10	60043	60043	60043	69190	60043
240024	60042	449	0	0	0	0	0	0	0	21	0	0	43	0	25	240010	10	240000	10	240000	50	2279971	1	60023	60042	60042	29996	0	3	30022	240010	20	240000	20	720000	60042	60042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	5	16	6	6	60039	0	240000	10	60043	60043	60043	60043	60043

TBL (four register table, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->6

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations