Firestorm: TBL (three register table, 16B) measurements

Code:

  tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	l1d cache writeback (a8)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
2004	4037	30	0	0	0	147	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038

Test 2: Latency 1->2

Code:

  tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	0	0	0	0	0	0	1020	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	1	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	1	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	726	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	3	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	3	39787	0	20000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	251	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	1	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	12	0	0	726	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	3	0	0	82	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->3

Code:

  tbl v1.16b, { v0.16b, v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	299	0	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40085	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	202	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	3	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	0	776	39687	25	20100	100	20000	100	20000	511	5717680	0	40018	40134	40085	37172	3	37495	20100	200	20000	200	60498	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40087
20204	40086	301	1	0	0	1	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20252	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	0	103	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	0	2056	0	710	1	3	16	2	2	39787	0	20000	100	40038	40038	40087	40134	40086
20204	40037	300	0	0	0	1	0	104	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	6	640	3	16	3	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	1	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	3	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39844	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	3	2	39787	20000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->4

Code:

  tbl v2.16b, { v0.16b, v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0039

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20039	150	27	12	0	61	19734	25	20104	100	20002	100	20000	500	2838987	20032	20063	20039	17207	3	17497	20100	200	20000	200	60000	20039	20063	1	1	10201	100	99	100	100	10000	100	710	0	2	16	2	2	19876	0	20000	100	20040	20040	20040	20040	20040
20204	20054	150	0	5	0	61	19739	25	20105	100	20002	100	20000	500	2835505	20020	20063	20051	17210	3	17524	20100	200	20000	200	60000	20039	20054	1	1	10201	100	99	100	100	10000	100	710	0	3	16	2	2	19864	0	20000	100	20052	20040	20064	20052	20064
20204	20063	150	348	2	0	61	19734	25	20102	100	20005	100	20000	500	2835365	20020	20039	20054	17195	3	17521	20100	200	20000	200	60000	20063	20063	1	1	10201	100	99	100	100	10000	100	710	0	2	16	2	2	19852	1	20000	100	20064	20052	20040	20040	20064
20204	20063	150	279	12	0	61	19718	25	20106	100	20004	100	20000	500	2838987	20020	20066	20063	17219	3	17521	20100	200	20000	200	60930	20054	20110	1	1	10201	100	99	100	100	10000	100	710	1	2	16	2	2	19864	0	20000	100	20040	20040	20040	20064	20040
20204	20051	150	0	4	0	61	19718	25	20101	100	20012	100	20000	500	2835389	20020	20039	20051	17195	3	17497	20100	200	20000	200	60000	20051	20039	1	1	10201	100	99	100	100	10000	100	710	1	2	16	2	2	19864	0	20000	100	20052	20040	20064	20052	20064
20204	20039	150	453	12	0	61	19718	25	20102	100	20005	100	20000	500	2835381	20032	20063	20063	17195	3	17497	20100	200	20000	200	60000	20063	20051	1	1	10201	100	99	100	100	10000	100	710	1	2	16	2	2	19864	0	20000	100	20040	20064	20052	20040	20052
20204	20039	150	69	3	1	61	19712	25	20102	100	20005	100	20000	500	2835381	20032	20063	20039	17207	3	17497	20100	200	20000	200	60000	20054	20063	1	1	10201	100	99	100	100	10000	100	710	1	2	16	2	2	19852	0	20000	100	20052	20040	20040	20040	20064
20204	20039	150	0	2	0	61	19718	25	20105	100	20012	100	20000	500	2837185	20020	20039	20063	17195	3	17512	20100	200	20000	200	60000	20054	20051	1	1	10201	100	99	100	100	10000	100	710	1	2	16	2	3	19876	0	20000	100	20064	20040	20064	20052	20040
20204	20060	150	12	6	0	61	19718	25	20112	100	20002	100	20000	500	2835505	20020	20063	20051	17195	3	17521	20100	200	20000	200	60000	20039	20039	1	1	10201	100	99	100	100	10000	100	710	1	2	16	2	2	19852	0	20000	100	20055	20052	20040	20064	20040
20204	20039	150	6	12	0	61	19718	25	20106	100	20005	100	20000	500	2835505	20020	20039	20051	17195	3	17497	20100	200	20000	200	60000	20063	20051	1	1	10201	100	99	100	100	10000	100	710	1	2	16	2	2	19864	0	20000	100	20052	20040	20064	20052	20052

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20039	151	42	0	13	251	19742	25	20016	10	20009	10	20000	50	2839418	20032	20063	20039	17217	3	17531	20010	20	20000	20	60000	20054	20054	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19874	20000	10	20064	20052	20064	20052	20064
20024	20051	150	0	0	5	61	19717	25	20017	10	20007	10	20000	50	2839418	20044	20039	20039	17232	3	17531	20010	20	20000	20	60000	20063	20054	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19862	20000	10	20052	20064	20052	20064	20052
20024	20051	150	21	0	5	61	19715	25	20018	10	20008	10	20000	50	2837185	20032	20054	20039	17217	3	17519	20010	20	20000	20	60000	20039	20066	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19874	20000	10	20064	20052	20052	20052	20064
20024	20051	150	0	0	9	61	19751	25	20023	10	20013	10	20000	50	2835365	20020	20051	20039	17238	3	17519	20010	20	20000	20	60000	20057	20054	1	1	10021	10	9	10	10	10000	10	0	0	0	15	640	3	16	2	3	19862	20000	10	20064	20052	20064	20052	20064
20024	20063	150	27	0	5	61	19715	25	20020	10	20009	10	20000	50	2838987	20032	20051	20039	17229	3	17531	20010	20	20000	20	60000	20063	20051	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	2	19862	20000	10	20064	20052	20052	20064	20040
20024	20039	150	0	0	5	61	19717	25	20020	10	20010	10	20000	50	2839418	20047	20051	20039	17217	3	17519	20010	20	20000	20	60000	20039	20066	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19862	20000	10	20040	20067	20040	20052	20058
20024	20039	151	3	0	9	61	19751	25	20023	10	20013	10	20000	50	2835513	20020	20051	20039	17235	3	17519	20010	20	20000	20	60000	20054	20051	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19877	20000	10	20040	20052	20040	20067	20040
20024	20039	150	24	352	5	61	19734	25	20016	10	20005	10	20000	50	2837185	20044	20063	20039	17217	3	17519	20010	20	20000	20	60000	20057	20054	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19868	20000	10	20052	20058	20064	20058	20052
20024	20051	150	0	0	13	61	19717	25	20017	10	20008	10	20000	50	2837185	20035	20054	20054	17229	3	17543	20010	20	20000	20	60000	20063	20051	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19874	20000	10	20064	20052	20064	20052	20067
20024	20066	150	0	0	5	61	19734	25	20022	10	20012	10	20000	50	2837185	20032	20054	20051	17229	3	17531	20010	20	20000	20	60000	20051	20063	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19874	20000	10	20052	20064	20052	20052	20064

Test 5: Latency 1->5

Code:

  tbl v3.16b, { v0.16b, v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	0	0	0	0	0	0	726	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	0	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	76	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	0	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39687	25	20100	100	20000	103	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	6	4	0	0	710	0	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	88	0	104	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	0	2	16	2	0	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	2	0	0	0	0	726	1	3	26	2	2	39787	0	20000	100	40038	40038	40086	40038	40038
20204	40037	301	1	0	1	0	88	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	3	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	3	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	12	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	0	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	726	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	7	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	0	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	0	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	0	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	0	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	1	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	0	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	0	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	3	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	0	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	0	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038

Test 6: throughput

Count: 8

Code:

  tbl v0.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v1.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v2.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v3.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v4.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v5.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v6.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v7.16b, { v8.16b, v9.16b, v10.16b }, v11.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40063	300	0	0	0	342	25	160100	100	160000	100	160000	500	1599960	0	40023	0	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	1	1	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	44	25	160100	100	160000	100	160000	500	1599960	1	40023	0	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	44	25	160100	100	160000	100	160000	500	1599960	0	40023	0	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	709	25	160100	100	160000	100	160000	500	1599960	1	40023	0	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	3	0	5110	1	16	1	1	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	67	25	160100	100	160000	100	160000	500	1599960	1	40023	0	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	199	25	160100	100	160000	100	160000	500	1599960	1	40023	0	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	197	25	160100	100	160000	100	160000	500	1599960	0	40023	0	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	12	195	25	160100	100	160000	100	160000	500	1599960	1	40023	0	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	67	25	160100	100	160000	100	160000	500	1599960	0	40023	0	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	44	25	160100	100	160000	100	160000	500	1599960	0	40023	0	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	40039	160000	100	40043	40043	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40052	299	0	0	0	0	0	0	0	0	0	708	25	160010	10	160000	10	160000	50	1599960	0	40023	40042	40042	19996	0	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	17	16	16	6	0	40039	0	0	0	160000	10	40095	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	0	0	5529	25	160010	10	160000	10	160000	50	1599960	1	40023	40042	40042	19996	0	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	17	16	16	6	0	40039	0	0	0	160000	10	40043	40043	40043	40043	40043
160024	40042	299	0	0	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	1	40023	40042	40042	19996	0	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	16	16	6	16	0	40039	0	0	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	1	40023	40042	40042	19996	0	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	16	16	6	16	0	40039	0	0	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	1	40023	40042	40042	19996	0	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	16	16	6	16	0	40039	0	0	0	160000	10	40043	40043	40043	40043	40043
160024	40042	299	0	0	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	1	40023	40042	40042	19996	0	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	6	16	6	13	0	40039	0	0	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	1	40023	40042	40042	19996	0	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	13	16	16	6	0	40039	0	0	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	1	40023	40042	40042	19996	0	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	16	16	13	16	0	40039	0	0	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	1	40023	40042	40042	19996	0	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	16	16	16	6	0	40039	0	0	0	160000	10	40043	40043	40043	40043	40043
160024	40042	299	0	0	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	1	40023	40042	40042	19996	0	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	6	16	16	6	0	40039	0	0	0	160000	10	40043	40043	40043	40043	40043

TBL (three register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations