Firestorm: TBL (three register table, 8B) measurements

Code:

  tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v3.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
2004	4037	30	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	84	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	117	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	31	21	159	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	3	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	51	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	61	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	3	156	3687	25	2000	2000	2000	551680	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038

Test 2: Latency 1->2

Code:

  tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v3.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	0	0	0	584	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	0	3	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	102	20304	533	5718963	1	40018	40131	40184	37173	3	37554	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	2	2	0	0	710	0	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	1	0	0	103	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	0	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	2175	710	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	712	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	82	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10202	100	99	100	100	10000	100	0	0	0	0	712	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	299	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	191	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	346	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	0	640	3	16	3	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	18	0	0	640	3	16	3	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	144	192	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	6	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	0	0	640	3	16	3	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	4	39787	20000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->3

Code:

  tbl v1.8b, { v0.16b, v1.16b, v2.16b }, v3.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	299	0	0	0	0	61	39687	25	20100	100	20000	107	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	1	0	710	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	124	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	726	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	1	0	710	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	4	0	710	1	2	16	2	2	39787	20000	100	40038	40038	40084	40038	40038
20204	40037	300	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	14	180	710	1	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	0	61	39687	25	20100	100	20000	102	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	71	6	710	1	3	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	56	0	710	1	2	16	2	2	39824	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	53	0	710	1	2	16	3	3	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	1	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	68	12	710	1	2	16	2	3	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	0	61	39687	25	20100	100	20000	100	20152	500	5717680	1	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	69	3	710	1	2	16	3	2	39787	20000	100	40038	40038	40038	40086	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	2	3	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	6	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	6	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	226	39687	25	20010	10	20000	10	20000	50	5717680	1	40066	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	56	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	5555	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	36	6	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	726	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	37	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	3	3	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	314	0	315	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->4

Code:

  tbl v2.8b, { v0.16b, v1.16b, v2.16b }, v3.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20039	150	0	0	0	0	0	1	0	61	19718	25	20106	100	20013	100	20000	500	2835358	0	20047	20066	20066	17202	6	17493	20100	200	20008	200	60024	20054	20066	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	716	0	0	16	0	1	19875	0	20000	100	20100	20040	20055	20064	20040
20204	20039	150	0	0	0	0	0	5	0	61	19751	25	20112	100	20013	100	20000	500	2837615	0	20044	20051	20039	17217	6	17520	20100	200	20008	200	60024	20039	20054	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	716	0	0	16	0	0	19860	0	20000	100	20067	20040	20040	20055	20040
20204	20039	150	0	0	0	0	0	13	0	61	19751	25	20113	100	20006	100	20885	511	2839418	0	20035	20054	20039	17202	6	17493	20100	200	20008	200	60024	20079	20066	1	1	10201	100	99	100	100	10000	100	0	40	102	1	1	1	716	0	1	16	0	0	19875	0	20000	100	20067	20055	20067	20055	20040
20204	20039	150	0	0	0	0	0	13	0	61	19736	25	20107	100	20007	100	20000	500	2843188	0	20047	20066	20066	17226	6	17508	20100	200	20008	200	60024	20066	20039	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	716	0	1	16	0	0	19887	0	20000	100	20055	20067	20040	20040	20040
20204	20066	150	0	0	0	0	0	6	0	61	19751	25	20113	100	20013	100	20000	500	2835482	0	20020	20039	20051	17217	6	17520	20100	200	20008	200	60024	20054	20039	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	0	710	1	2	16	2	2	19879	0	20000	100	20052	20052	20040	20052	20055
20204	20066	150	0	0	0	0	0	9	0	61	19718	25	20105	100	20007	100	20000	500	2839418	0	20047	20039	20054	17210	3	17524	20100	200	20000	200	60000	20054	20039	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	19852	0	20000	100	20055	20067	20052	20040	20067
20204	20039	150	0	0	0	0	0	13	0	61	19748	25	20113	100	20013	100	20000	500	2839418	0	20020	20054	20066	17222	3	17512	20100	200	20000	200	60000	20160	20078	1	1	10201	100	99	100	100	10000	100	0	58	0	0	0	0	710	1	2	16	2	2	19864	0	20000	100	20064	20067	20040	20067	20067
20204	20054	150	0	0	0	0	0	13	0	61	19698	25	20105	100	20116	111	20000	500	2837709	0	20035	20066	20039	17195	3	17497	20100	200	20000	200	60000	20054	20063	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	19879	0	20000	100	20067	20067	20080	20067	20067
20204	20039	150	0	0	0	0	0	6	0	61	19717	25	20109	100	20005	100	20000	500	2838987	0	20035	20054	20039	17222	3	17497	20100	200	20000	200	60000	20066	20066	1	1	10201	100	99	100	100	10000	100	0	50	0	0	0	0	710	1	2	16	2	2	19867	0	20000	100	20100	20067	20040	20040	20040
20204	20063	150	0	0	0	0	0	5	0	61	19718	25	20105	100	20006	100	20000	500	2838987	0	20035	20051	20063	17210	3	17512	20100	200	20000	200	60000	20054	20066	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	3	19876	0	20000	100	20067	20040	20064	20084	20064

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20039	150	0	0	0	0	0	0	5	0	61	19734	25	20022	10	20007	10	20000	50	2837185	1	20047	20066	20039	17232	3	17534	20010	20	20000	20	60000	20063	20051	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	21	0	0	640	2	16	2	2	19862	0	20000	10	20052	20064	20052	20052	20052
20024	20051	151	0	0	0	0	0	0	6	0	61	19748	25	20017	10	20012	10	20295	50	2835365	1	20044	20063	20051	17241	3	17543	20010	20	20000	20	60000	20039	20063	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	117	0	0	640	2	16	2	2	19865	0	20000	10	20064	20052	20064	20052	20055
20024	20039	150	0	0	0	0	0	0	6	0	61	19734	25	20015	10	20012	10	20000	50	2837185	1	20032	20051	20039	17241	3	17543	20010	20	20000	20	60000	20063	20051	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	15	0	0	640	2	16	2	1	19862	0	20000	10	20055	20052	20040	20115	20040
20024	20063	150	0	0	0	0	0	0	5	0	251	19717	25	20017	10	20007	10	20000	50	2837185	0	20032	20063	20051	17229	3	17531	20010	20	20000	20	60000	20054	20063	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	165	0	0	640	2	16	2	2	19862	0	20000	10	20052	20040	20064	20055	20040
20024	20054	150	0	0	0	0	0	0	7	0	61	19734	25	20022	10	20012	10	20000	50	2838987	1	20032	20051	20051	17229	3	17531	20010	20	20000	20	60000	20063	20039	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	640	2	16	2	2	19862	0	20000	10	20064	20052	20064	20052	20064
20024	20051	150	0	0	0	0	0	0	6	0	61	19734	25	20015	10	20007	10	20000	50	2837185	0	20032	20066	20039	17217	3	17531	20010	20	20000	20	60000	20063	20051	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	177	0	0	640	2	16	2	2	19874	0	20000	10	20067	20040	20064	20052	20052
20024	20051	150	0	0	0	0	0	0	5	0	61	19734	25	20019	10	20001	10	20000	50	2835356	0	20020	20039	20051	17229	3	17531	20010	20	20000	20	60000	20066	20039	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	108	0	0	640	2	16	2	2	19862	0	20000	10	20052	20040	20052	20040	20052
20024	20051	150	0	0	0	0	0	0	12	0	61	19734	25	20015	10	20001	10	20000	50	2837185	1	20020	20039	20051	17229	3	17531	20010	20	20000	20	60000	20039	20051	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	2	2	19874	0	20000	10	20064	20052	20064	20052	20040
20024	20039	150	0	0	0	0	0	0	5	0	251	19718	25	20016	10	20005	10	20000	50	2835356	0	20044	20051	20063	17241	3	17531	20010	20	20000	20	60000	20051	20063	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	640	2	16	2	2	19874	0	20000	10	20064	20052	20064	20052	20052
20024	20051	150	0	0	0	0	0	0	12	0	61	19734	25	20022	10	20012	10	20000	50	2837185	1	20032	20051	20051	17229	3	17543	20010	20	20000	20	60000	20054	20051	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	3	0	0	640	2	16	2	2	19862	0	20000	10	20052	20040	20052	20040	20064

Test 5: Latency 1->5

Code:

  tbl v3.8b, { v0.16b, v1.16b, v2.16b }, v3.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	4	40018	0	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	5	4	4	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	4	40018	3	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	5	0	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	4	40018	0	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	5	0	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	82	39687	25	20100	100	20000	100	20000	500	5717680	1	4	40018	0	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	5	0	3	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	777	39687	25	20100	100	20000	100	20000	500	5717680	1	4	40018	0	40037	40037	37172	7	37512	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	5	0	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	4	40018	0	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	5	0	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	0	84	39687	25	20100	100	20000	100	20000	500	5717680	1	4	40018	0	40037	40037	37172	25	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	21	710	5	0	2	16	2	3	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	4	40018	0	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	5	0	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	4	40018	0	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	5	0	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	0	61	39687	45	20100	100	20000	100	20000	500	5717680	1	4	40018	0	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	5	0	2	16	2	2	39787	20000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	bd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39787	20000	10	40085	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39847	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40085	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	145	39687	25	20010	10	20000	10	20000	50	5717680	1	40378	40464	40474	37216	40	37673	21226	20	21316	20	64920	40575	40326	8	1	10021	10	9	10	10	10000	10	2	18013	0	798	6	125	6	6	40212	20000	10	40426	40526	40521	40574	40716
20024	40524	304	2	1	1	61	39687	25	20010	10	20000	14	21368	61	5717680	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	44785	40037	1	1	10021	10	9	10	10	10000	10	0	0	20	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5718066	1	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	61	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038

Test 6: throughput

Count: 8

Code:

  tbl v0.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  tbl v1.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  tbl v2.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  tbl v3.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  tbl v4.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  tbl v5.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  tbl v6.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  tbl v7.8b, { v8.16b, v9.16b, v10.16b }, v11.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40063	300	0	0	0	0	0	44	25	160100	100	160000	100	160000	500	1599960	1	40023	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	18	2	0	0	5110	3	16	3	3	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	0	0	44	102	160100	100	160000	100	160000	500	1599960	1	40023	40042	40042	19973	3	20088	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	3	16	2	3	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	0	0	86	25	160405	100	160000	100	160000	500	1599960	1	40023	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	3	16	3	3	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	0	0	65	25	160100	100	160000	100	160000	500	1599960	0	40023	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	3	44	3	3	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	0	0	44	25	160100	100	160000	100	160000	500	1599960	0	40023	40042	40042	19973	3	20118	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	3	16	3	3	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	1	0	0	0	0	44	25	160100	100	160000	100	160000	500	1599960	0	40023	40042	40042	19973	3	20029	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	3	16	3	3	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	0	0	107	25	160100	100	160000	100	160000	500	1599960	0	40023	40042	40042	19973	3	20000	160100	200	160000	200	480000	40096	40042	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	2	16	3	3	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	0	0	44	25	160100	100	160000	100	160000	500	1599960	0	40023	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	3	16	3	3	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	300	0	0	0	0	0	44	25	160100	100	160000	100	160000	500	1599960	0	40023	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	3	16	2	3	40039	160000	100	40043	40043	40043	40043	40043
160204	40042	299	0	0	0	0	0	44	25	160100	100	160000	100	160000	500	1599960	0	40023	40042	40042	19973	3	20000	160100	200	160000	200	480000	40042	40042	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	3	16	3	3	40039	160000	100	40043	40043	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40052	299	0	0	0	0	0	0	0	127	25	160010	10	160000	10	160000	50	1599960	0	1	40023	40042	40042	19996	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	2	16	0	3	2	2	40039	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	0	0	40023	40042	40042	19996	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	2	16	0	0	3	3	40039	0	160000	10	40043	40043	40043	40095	40043
160024	40042	300	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	0	0	40023	40042	40042	19996	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	2	16	0	0	2	2	40039	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	0	0	40023	40042	40042	19996	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	3	0	0	5020	2	16	0	2	2	2	40039	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	0	0	40023	40042	40042	19996	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	2	16	0	2	2	2	40039	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	0	0	40023	40042	40042	19996	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	2	16	0	0	2	2	40039	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	0	0	40023	40042	40042	19996	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	2	16	0	2	3	2	40039	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	0	0	40023	40042	40042	19996	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	2	16	0	2	2	3	40039	0	160000	10	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	43	25	160010	10	160000	10	160000	50	1599960	0	0	40023	40042	40042	19996	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	2	16	0	1	2	2	40039	0	160000	10	40043	40043	40043	40043	40043
160024	40042	299	0	0	0	0	0	0	0	85	25	160010	10	160000	10	160000	50	1599960	0	0	40023	40042	40042	19996	3	20022	160010	20	160000	20	480000	40042	40042	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	0	5020	2	16	0	0	3	2	40039	0	160000	10	40043	40043	40043	40043	40043

TBL (three register table, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations