Firestorm: TBL (two register table, 16B) measurements

Code:

  tbl v0.16b, { v0.16b, v1.16b }, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	72	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  tbl v0.16b, { v0.16b, v1.16b }, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	57	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	3	16	2	3	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	12	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	2	0	0	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	369	132	0	103	19687	25	10100	100	10000	100	10608	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	3	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	3	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	3	0	0	61	19687	25	10100	113	10000	100	10000	500	2847680	1	20054	20037	20037	18430	3	18745	10100	202	10000	200	30492	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	6	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	18	0	0	61	19687	44	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	6001	0	712	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20230
10204	20037	149	0	0	0	69	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	18	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	3	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	18	0	0	631	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	712	1	2	16	2	2	19913	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	42	0	0	103	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20179	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	6	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10022	10	10012	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	1	16	2	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	24	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	15	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	39	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	685	2	16	2	2	19785	10000	10	20038	20038	20085	20228	20276
10024	20226	152	1	0	0	5	594	352	2015	19632	98	10070	12	10000	10	10152	72	2854095	20162	20273	20273	18459	20	18786	10772	22	10825	22	32511	20276	20226	6	1	10021	10	9	10	10	10000	10	2	2	0	0	8213	4	0	0	746	6	48	4	2	20003	10000	10	20275	20228	20276	20275	20271
10024	20274	152	1	1	5	4	684	440	2446	19643	117	10058	10	10012	12	10760	50	2854095	20162	20227	20262	18453	26	18859	10774	22	10835	20	31998	20313	20272	6	1	10021	10	9	10	10	10000	10	2	2	0	0	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20276
10024	20226	151	1	0	5	5	609	508	2463	19643	99	10075	12	10060	10	10760	83	2854095	20198	20272	20227	18459	24	18854	10770	20	10674	20	31476	20276	20273	6	1	10021	10	9	10	10	10000	10	0	2	0	1	0	7	0	0	745	3	42	3	3	20017	10000	10	20319	20277	20274	20264	20320
10024	20272	152	1	1	3	6	996	528	2964	19621	134	10048	14	10072	10	10912	72	2855378	20234	20322	20320	18468	21	18842	10922	24	11001	20	31482	20275	20320	6	1	10021	10	9	10	10	10000	10	0	0	2	1	11970	2	0	0	766	2	77	2	2	20075	10000	10	20368	20418	20411	20277	20459

Test 3: Latency 1->3

Code:

  tbl v1.16b, { v0.16b, v1.16b }, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	1	0	0	1	0	0	0	9	0	1	98	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	713	0	4	16	4	5	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	1	0	0	0	0	0	1	70	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	713	0	5	16	4	4	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	1	0	0	0	0	0	1	540	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	713	0	6	16	5	5	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	1	0	0	0	0	0	1	65	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	713	0	5	16	5	5	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	1	0	0	0	12	0	1	65	19687	25	10100	100	10000	100	10000	500	2847680	0	20054	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	713	0	5	16	5	3	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	1	0	0	1	0	0	0	0	0	1	86	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10174	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	716	0	3	16	3	5	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	1	0	0	0	18	0	1	65	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	713	0	3	16	5	5	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	1	0	0	0	3	0	2	70	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	713	0	3	16	6	6	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	1	0	0	0	0	0	1	65	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	713	0	3	16	6	3	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	1	0	0	0	12	0	1	65	19687	43	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	713	0	4	16	4	4	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	12	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	640	2	16	2	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	3	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	210	88	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	640	2	16	3	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	640	2	16	3	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	27	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20037	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	237	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	640	2	16	3	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	9	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->4

Code:

  tbl v2.16b, { v0.16b, v1.16b }, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	42	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	168	61	19687	25	10100	104	10000	100	10152	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	3	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	9	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	270	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	61	19687	20021	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	20021	25	10010	10	10000	10	10000	50	2847680	0	20021	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	27	0	61	19687	20021	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20085	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	0	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	0	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	24	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	6	0	61	19687	0	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	3	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	0	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	0	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	0	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	12	0	189	19687	0	44	10046	10	10000	10	10000	50	2847680	1	20018	20037	20037	18451	3	18767	10010	20	10169	20	30000	20276	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  tbl v0.16b, { v8.16b, v9.16b }, v10.16b
  tbl v1.16b, { v8.16b, v9.16b }, v10.16b
  tbl v2.16b, { v8.16b, v9.16b }, v10.16b
  tbl v3.16b, { v8.16b, v9.16b }, v10.16b
  tbl v4.16b, { v8.16b, v9.16b }, v10.16b
  tbl v5.16b, { v8.16b, v9.16b }, v10.16b
  tbl v6.16b, { v8.16b, v9.16b }, v10.16b
  tbl v7.16b, { v8.16b, v9.16b }, v10.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20058	150	0	0	1	1	132	88	40	25	80286	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	240000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1745	5110	2	16	1	1	20035	0	80000	100	20039	20039	20089	20088	20039
80204	20038	150	0	0	0	0	12	0	40	25	80194	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	240000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	2	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	240000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5128	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	240000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	51	0	9	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	240000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	240000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	240000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	240000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	5	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	240000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	61	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	240000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l2 tlb miss data (0b)	19	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20048	150	1	0	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	240000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	3	0	5020	20	16	23	18	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	240000	20038	20038	1	1	80021	10	9	10	10	80000	10	1	0	0	5020	23	16	19	23	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	240000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	19	16	23	19	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	240000	20038	20038	1	1	80021	10	9	10	10	80000	10	1	0	0	5020	23	16	19	23	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	240000	20038	20038	1	1	80021	10	9	10	10	80000	10	1	0	0	5020	20	16	23	20	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	1	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	240000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	19	16	23	18	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	240000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	17	16	22	18	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	739	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	240000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	23	16	14	23	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	240000	20038	20038	1	1	80021	10	9	10	10	80000	10	2	3	0	5020	13	16	23	14	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	240000	20038	20038	1	1	80021	10	9	10	10	80000	10	8	0	0	5020	23	16	23	23	20035	80000	10	20039	20039	20039	20039	20039

TBL (two register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations