Firestorm: TBX (four register table, 16B) measurements

Code:

  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 4.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
4004	8037	60	0	0	30	61	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	73	2	16	1	1	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	312	61	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	73	1	16	1	1	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	61	7687	25	4000	4000	4000	1125680	1	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	73	1	16	1	1	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	61	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	73	1	16	1	1	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	6	61	7687	25	4000	4000	4000	1125680	1	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	73	1	16	1	1	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	61	7687	25	4000	4000	4000	1125680	1	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	73	1	16	1	1	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	63	61	7687	25	4000	4000	4000	1125680	1	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	73	1	16	1	1	7929	4000	8038	8038	8038	8038	8038
4004	8037	60	1	1	0	61	7687	25	4000	4000	4000	1125680	1	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	73	1	16	1	1	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	61	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	73	1	16	1	1	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	61	7687	25	4000	4000	4000	1125680	1	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	73	1	16	1	1	7796	4000	8038	8038	8038	8038	8038

Test 2: Latency 1->1

Code:

  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	80037	600	0	0	0	0	726	79687	25	40100	100	40000	100	40000	500	11457680	0	80018	0	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	17	1	2	79797	40000	100	80038	80038	80038	80038	80038
40204	80037	599	0	0	0	0	251	79687	25	40100	100	40000	100	40000	500	11457680	0	80018	0	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	17	1	1	79797	40000	100	80038	80038	80038	80038	80038
40204	80037	600	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	0	80018	0	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	17	1	1	79797	40000	100	80038	80038	80038	80038	80038
40204	80037	599	0	0	39	0	61	79687	25	40100	100	40000	100	40000	500	11457680	0	80018	0	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	52	0	0	710	0	1	17	1	1	79797	40000	100	80038	80038	80038	80038	80038
40204	80037	599	0	0	21	0	61	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	0	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	710	0	1	17	1	1	79797	40000	100	80038	80038	80038	80038	80038
40204	80037	599	0	0	6	0	61	79687	25	40100	100	40000	100	40000	500	11457680	0	80018	0	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	17	1	1	79797	40000	100	80038	80038	80038	80038	80038
40204	80037	600	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	0	80018	0	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	17	1	1	79858	40000	100	80038	80038	80038	80038	80038
40204	80037	600	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	0	80018	0	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10202	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	17	1	1	79797	40000	100	80038	80038	80038	80038	80038
40204	80037	599	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	0	80018	0	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	2	34	0	0	710	0	1	17	1	1	79797	40000	100	80038	80038	80038	80038	80038
40204	80037	600	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	0	80018	0	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	17	1	0	79797	40000	100	80038	80038	80038	80038	80038

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	80037	600	0	0	0	346	79687	25	40010	10	40000	10	40000	50	11457680	1	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	649	1	17	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	0	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80084	1	1	10021	10	9	10	10	10000	10	0	0	3	0	649	1	17	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	600	0	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	1	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	649	1	17	1	79797	40000	10	80038	80038	80038	80038	80083
40024	80037	599	0	0	0	126	79687	25	40010	10	40000	10	40000	50	11457680	0	80018	80177	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	649	1	17	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	600	0	0	0	61	79687	25	40010	10	40000	10	40000	50	11458230	0	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	649	1	17	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	600	0	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	0	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	649	1	17	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	1	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	649	1	17	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	1	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	1	0	0	649	1	17	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	1	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	649	1	17	4	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	600	0	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	0	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	649	1	17	1	79797	40000	10	80038	80038	80038	80038	80038

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60204	100038	749	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	1910	0	1	17	1	1	99798	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	1910	0	1	17	1	1	99798	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	1910	0	1	17	1	1	99798	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	2	0	43	0	0	2	0	0	0	1910	0	1	17	1	1	99798	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	726	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	1910	0	1	17	1	1	99866	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	1910	0	1	17	1	1	99798	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	329	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100088	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	1910	0	1	17	1	1	99798	60000	100	100039	100039	100039	100039	100039
60204	100038	750	0	0	0	0	726	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	1910	0	1	17	1	1	99798	60000	100	100039	100039	100039	100039	100039
60204	100038	749	4	0	0	0	1610	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	8051	0	0	0	0	1910	0	1	17	1	1	99798	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	1910	0	1	17	1	1	99798	60000	100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60024	100038	749	0	0	0	0	0	0	0	103	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	0	100038	100038	89662	3	90019	50010	20	50000	20	140000	100038	100038	2	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	0	1899	1	17	0	1	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	100019	0	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	0	1899	1	17	0	1	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	750	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	100019	0	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	0	1899	1	17	0	1	99798	60000	10	100039	100039	100039	100090	100039
60024	100038	749	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	0	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	0	1899	1	17	0	1	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	0	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	0	1899	1	17	0	1	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	61	99686	26	50010	10	50024	10	50000	50	14327648	1	100019	0	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1	0	1899	1	17	0	1	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	100019	0	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	0	1899	1	17	0	1	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	778	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	100019	0	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	3	0	0	0	1899	1	17	0	1	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	750	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	100019	0	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1	0	0	0	1	0	1899	1	17	0	1	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	100019	0	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	0	1899	1	17	0	1	99798	60000	10	100039	100090	100039	100039	100039

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60204	80043	600	0	0	0	0	0	0	0	94	79682	26	50101	100	50000	100	50000	500	11447447	0	80021	0	80043	80040	69704	3	70021	50100	200	50000	200	140000	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	2	0	0	0	0	0	1	1910	1	17	1	1	79821	0	60000	100	80041	80041	80041	80041	80041
60204	80040	600	0	0	0	0	0	0	0	61	79682	26	50100	100	50000	100	50000	500	11447447	1	80021	0	80043	80040	69704	3	70021	50100	200	50000	200	140000	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	79821	0	60000	100	80041	80041	80041	80041	80044
60204	80043	599	0	0	0	0	0	0	0	61	79686	26	50103	100	50003	100	50000	500	11447447	0	80021	0	80040	80040	69704	3	70021	50100	200	50000	200	140000	80043	80043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	79821	0	60000	100	80041	80041	80041	80041	80041
60204	80043	599	0	0	0	0	0	0	0	2450	79605	72	50298	104	50250	104	50945	533	11454179	0	80021	0	80043	80040	69707	3	70021	50100	200	50000	200	140000	80043	80043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	79821	0	60000	100	80041	80041	80041	80044	80041
60204	80040	599	0	0	0	0	0	0	1	61	79682	26	50100	100	50000	100	50000	500	11447938	1	80021	0	80040	80040	69704	3	70024	50100	200	50000	200	140000	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	79824	0	60000	100	80041	80041	80041	80044	80044
60204	80040	599	0	0	0	0	0	0	0	61	79682	26	50100	100	50000	100	50000	500	11447447	0	80021	0	80040	80043	69704	3	70021	50100	200	50000	200	140000	80040	80040	5	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	79821	0	60000	100	80041	80041	80041	80044	80041
60204	80040	600	0	0	0	0	0	0	0	726	79682	26	50100	100	50003	100	50000	500	11447447	1	80021	0	80043	80040	69704	3	70021	50100	200	50000	200	140000	80043	80043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	79821	0	60000	100	80041	80041	80041	80041	80041
60204	80040	600	0	0	0	0	0	0	0	61	79686	26	50100	100	50003	100	50000	500	11447447	1	80021	0	80043	80040	69704	3	70021	50100	200	50000	200	140000	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	79824	0	60000	100	80041	80041	80044	80041	80041
60204	80040	600	0	0	0	0	0	0	0	61	79682	26	50100	100	50000	100	50000	500	11447447	1	80024	0	80040	80043	69704	3	70021	50100	200	50000	200	140000	80040	80043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	79821	0	60000	100	80041	80041	80041	80041	80041
60204	80043	600	0	0	0	0	0	0	1	61	79685	26	50100	100	50000	100	50000	500	11447447	1	80021	0	80040	80040	69704	3	70021	50100	200	50000	200	140000	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1	0	1910	1	17	1	1	79824	0	60000	100	80041	80041	80041	80041	80041

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60024	80040	600	0	0	61	79682	26	50010	10	50001	10	50000	50	11447447	0	1	80021	0	80043	80040	69704	0	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1899	0	6	17	0	0	0	4	6	79821	0	0	60000	10	80041	80041	80041	80041	80041
60024	80040	600	0	2	61	79682	26	50010	10	50000	10	50000	50	11447447	0	1	80021	0	80040	80040	69704	0	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1899	0	7	17	0	0	0	6	7	79821	0	0	60000	10	80041	80044	80041	80044	80044
60024	80040	599	0	1	61	79682	26	50010	10	50000	10	50000	50	11447447	0	0	80021	0	80040	80040	69707	0	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1899	0	5	17	0	0	0	4	5	79821	0	0	60000	10	80041	80041	80041	80041	80041
60024	80040	599	0	0	61	79682	26	50010	10	50000	10	50000	50	11447447	0	0	80024	0	80040	80040	69704	0	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1899	0	6	17	0	0	0	5	6	79821	0	0	60000	10	80041	80041	80041	80041	80041
60024	80040	600	585	1	61	79682	26	50012	10	50001	10	50000	50	11447458	0	0	80021	0	80040	80040	69718	0	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1899	0	7	17	0	0	0	5	7	79821	0	0	60000	10	80041	80041	80041	80044	80041
60024	80040	600	0	0	61	79682	26	50011	10	50000	10	50000	50	11447447	0	1	80021	0	80040	80040	69704	0	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1899	0	7	17	0	0	0	4	5	79821	0	0	60000	10	80041	80044	80041	80044	80041
60024	80040	600	0	1	726	79682	26	50012	10	50002	10	50000	50	11447447	0	1	80024	0	80040	80040	69704	0	3	70021	50010	20	50000	20	140000	80040	80043	1	1	30021	10	9	10	10	30000	10	0	0	0	3	0	0	1899	0	7	17	0	0	0	5	7	79821	0	0	60000	10	80044	80041	80044	80041	80041
60024	80040	599	0	0	726	79685	26	50010	10	50000	10	50000	50	11447447	0	1	80021	0	80040	80040	69704	0	3	70021	50010	20	50000	20	140000	80043	80040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1899	0	7	17	0	0	0	6	4	79821	0	0	60000	10	80041	80041	80041	80041	80041
60024	80040	599	0	0	61	79682	26	50011	10	50000	10	50000	50	11447447	0	1	80021	0	80040	80040	69704	0	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1899	0	7	17	0	0	0	3	8	79821	0	0	60000	10	80041	80044	80041	80044	80041
60024	80040	620	0	0	61	79682	26	50013	10	50001	10	50000	50	11447447	0	1	80021	0	80040	80040	69704	0	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1899	0	6	17	0	0	0	5	6	79821	0	0	60000	10	80041	80041	80041	80041	80041

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0042

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60204	60042	449	0	0	0	61	59679	26	50101	100	50000	100	50000	500	8565351	1	60035	0	60054	60042	49718	3	50026	50100	200	50000	200	140000	60048	60042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59865	0	60000	100	60043	60055	60043	60055	60043
60204	60042	450	0	0	2	61	59686	26	50104	100	50004	100	50000	500	8564497	1	60023	0	60042	60054	49727	3	50035	50100	200	50000	200	140000	60054	60042	1	1	30201	100	99	100	100	30000	100	9	0	0	0	1910	1	17	1	1	59865	0	60000	100	60055	60043	60055	60043	60055
60204	60054	450	0	9	0	61	59679	26	50104	100	50004	100	50000	500	8564469	1	60023	0	60048	60048	49715	3	50023	50100	200	50000	200	140000	60054	60042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59865	0	60000	100	60043	60055	60043	60055	60043
60204	60042	450	0	0	4	61	59686	26	50104	100	50004	100	50000	500	8564469	1	60023	0	60042	60048	49715	3	50023	50100	200	50000	200	140000	60042	60054	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59859	0	60000	100	60055	60043	60055	60043	60055
60204	60054	449	0	0	1	66	59686	26	50104	100	50004	100	50000	500	8564497	0	60035	0	60054	60042	49715	3	50029	50100	200	50000	200	140000	60042	60054	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59865	0	60000	100	60043	60055	60043	60055	60043
60204	60054	449	0	0	0	61	59686	26	50104	100	50004	100	50000	500	8564497	1	60023	0	60054	60042	49715	3	50023	50100	200	50000	200	140000	60042	60054	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59859	0	60000	100	60055	60043	60110	60043	60043
60204	60042	450	0	0	4	61	59679	26	50101	100	50000	100	50000	500	8565609	1	60035	0	60054	60042	49715	3	50023	50100	200	50000	200	140000	60042	60054	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59865	0	60000	100	60049	60043	60049	60055	60043
60204	60042	450	0	0	1	61	59686	26	50104	100	50004	100	50000	500	8564801	0	60023	0	60054	60042	49715	3	50023	50848	200	50000	200	140000	60054	60042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59853	0	60000	100	60055	60043	60055	60046	60055
60204	60054	450	0	0	2	61	59679	26	50104	100	50000	100	50000	500	8565609	1	60035	0	60054	60042	49715	3	50023	50100	200	50000	200	140000	60042	60054	1	1	30201	100	99	100	100	30000	100	1	0	0	0	1910	1	17	1	1	59865	0	60000	100	60055	60043	60055	60043	60043
60204	60042	450	0	0	0	726	59686	26	50104	100	50004	100	50000	500	8564469	1	60023	0	60042	60054	49727	3	50035	50100	200	50000	200	140000	60054	60042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59853	0	60000	100	60055	60043	60055	60043	60055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0045

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60024	60045	450	0	0	0	0	0	61	59679	26	50011	10	50001	10	50000	50	8564469	1	60026	60042	60054	49715	3	50029	50010	20	50000	20	140000	60048	60042	1	1	30021	10	9	10	10	30000	10	0	0	0	1899	6	17	3	3	59853	0	60000	10	60043	60043	60043	60043	60055
60024	60118	466	1	1	1	9	0	61	59679	26	50014	10	50000	10	50000	50	8564469	0	60029	60048	60054	49727	3	50035	50010	20	50000	20	140000	60042	60054	1	1	30021	10	9	10	10	30000	10	0	0	0	1899	4	17	2	4	59865	0	60000	10	60043	60055	60043	60055	60043
60024	60045	450	0	0	0	0	0	61	59679	26	50010	10	50002	10	50000	50	8565609	1	60035	60054	60042	49715	3	50023	50010	20	50000	20	140000	60042	60042	1	1	30021	10	9	10	10	30000	10	0	0	0	1899	3	17	3	4	59853	19	60000	10	60046	60043	60049	60049	60049
60024	60042	450	0	0	0	0	0	61	59681	26	50010	10	50001	10	50000	50	8565233	1	60026	60042	60054	49715	3	50023	50010	20	50000	20	140000	60042	60054	1	1	30021	10	9	10	10	30000	10	0	0	0	1899	4	17	3	4	59853	0	60000	10	60049	60043	60043	60043	60043
60024	60042	449	0	0	0	15	0	61	59679	26	50010	10	50000	10	50000	50	8565609	1	60035	60048	60042	49715	3	50023	50010	20	50000	20	140000	60048	60042	1	1	30021	10	9	10	10	30000	10	0	0	1	1899	4	17	3	3	59865	0	60000	10	60043	60055	60043	60055	60043
60024	60042	450	0	0	0	0	0	61	59686	26	50014	10	50004	10	50000	50	8564469	1	60029	60048	60042	49715	3	50023	50010	20	50000	20	140000	60048	60048	1	1	30021	10	9	10	10	30000	10	0	0	0	1899	4	17	3	4	59859	0	60000	10	60043	60043	60043	60049	60043
60024	60042	450	0	0	0	0	0	61	59686	26	50014	10	50004	10	50000	50	8564469	1	60029	60048	60054	49727	3	50035	50010	20	50000	20	140000	60042	60042	1	1	30021	10	9	10	10	30000	10	0	0	0	1899	4	17	2	4	59853	0	60000	10	60055	60099	60049	60049	60046
60024	60042	450	0	0	0	0	2	61	59679	26	50010	10	50000	10	50000	50	8564497	0	60029	60042	60048	49700	3	50029	50010	20	50000	20	140000	60048	60048	1	1	30021	10	9	10	10	30000	10	0	0	0	1899	4	17	2	3	59859	0	60000	10	60049	60055	60043	60043	60043
60024	60042	449	0	0	1	0	4	61	59686	26	50014	10	50004	10	50000	50	8564469	1	60023	60042	60054	49727	3	50035	50010	20	50000	20	140000	60042	60042	1	1	30021	10	9	10	10	30000	10	0	0	0	1899	4	17	2	4	59865	0	60000	10	60055	60043	60055	60043	60055
60024	60054	449	0	0	0	0	0	61	59686	26	50014	10	50004	10	50000	50	8564469	1	60023	60042	60054	49727	3	50035	50010	20	50000	20	140000	60042	60048	1	1	30021	10	9	10	10	30000	10	0	0	0	1899	4	17	3	3	59853	0	60000	10	60055	60043	60055	60046	60055

Test 6: Latency 1->5

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b
  add v4.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0731

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60204	40659	305	0	0	0	339	61	40331	26	50500	100	50339	100	50000	500	5775133	1	40802	40737	40704	30394	0	3	30613	50100	200	50000	200	140000	40791	40650	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	40662	60000	100	40663	40729	40801	40618	40723
60204	40782	305	0	0	0	354	61	40294	26	50433	100	50341	100	50000	500	5783455	1	40643	40728	40800	30364	0	3	30868	50100	200	50000	200	140000	40731	40701	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	40738	60000	100	40786	40624	40702	40633	40864
60204	40602	305	0	0	0	290	61	40288	26	50461	100	50408	100	50000	500	5800323	1	40748	40647	40659	30390	0	3	30670	50100	200	50000	200	140000	40608	40752	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	40594	60000	100	40789	40663	40825	40822	40768
60204	40647	305	0	0	0	386	61	40288	26	50389	100	50320	100	50000	500	5790312	1	40778	40647	40788	30511	0	3	30844	50100	200	50000	200	140000	40659	40677	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	40524	60000	100	40702	40693	40603	40750	40708
60204	40662	306	0	0	0	457	251	40286	26	50407	100	50349	100	50000	500	5784657	1	40676	40701	40692	30437	0	3	30721	50100	200	50000	200	140000	40797	40731	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	0	17	1	1	40512	60000	100	40867	40702	40693	40696	40798
60204	40686	305	0	0	12	357	103	40433	26	50461	100	50388	100	50000	500	5772958	1	40778	40788	40662	30458	0	3	30619	50100	200	50000	200	140000	40809	40773	1	1	30201	100	99	100	100	30000	100	1	0	0	0	0	0	1910	1	17	1	1	40638	60000	100	40825	40810	40774	40855	40798
60204	40641	304	0	0	0	361	61	40338	26	50528	100	50302	100	50000	500	5780896	1	40805	40821	40743	30412	0	3	30730	50100	200	50000	200	140000	40797	40731	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	40638	60000	100	40741	40798	40732	40723	40678
60204	40785	305	0	0	0	361	61	40426	26	50497	100	50376	100	50000	500	5776676	1	40778	40671	40887	30517	0	3	30679	50100	200	50000	200	140000	40740	40785	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	40638	60000	100	40678	40750	40723	40627	40888
60204	40779	305	0	0	0	341	61	40242	26	50454	100	50339	100	50000	500	5789033	1	40595	40737	40737	30484	0	3	30703	50100	200	50000	200	140000	40776	40632	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	40662	60000	100	40735	40741	40798	40732	40822
60204	40731	305	0	0	0	434	61	40369	26	50515	100	50393	100	50000	500	5758899	1	40718	40632	40797	30466	0	3	30778	50100	200	50000	200	140000	40611	40677	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	40674	60000	100	40693	40603	40750	40882	40690

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0104

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60024	40695	300	0	0	18	61	39694	26	50033	10	50031	10	50000	50	5690882	0	40076	0	40083	40131	29776	3	30127	50010	20	50000	20	140000	40236	40104	1	1	30021	10	9	0	10	10	30000	10	0	0	3	1899	4	17	2	3	39971	60000	10	40099	40078	40081	40063	40075
60024	40074	300	0	0	17	61	39685	26	50028	10	50027	10	50000	50	5687641	0	40076	0	40194	40194	29803	3	30058	50010	20	50000	20	140000	40086	40092	1	1	30021	10	9	0	10	10	30000	10	0	0	0	1899	3	17	2	3	40007	60000	10	40219	40093	40174	40087	40199
60024	40092	300	0	0	19	61	39694	26	50030	10	50018	10	50000	50	5689834	1	40067	0	40131	40071	29773	3	30070	50010	20	50000	20	140000	40068	40089	1	1	30021	10	9	0	10	10	30000	10	0	0	0	1899	2	17	2	3	39972	60000	10	40069	40210	40072	40246	40078
60024	40086	301	0	0	20	61	39791	26	50021	10	50020	10	50000	50	5686276	0	40070	0	40083	40131	29776	3	30079	50010	20	50000	20	140000	40107	40200	1	1	30021	10	9	0	10	10	30000	10	0	0	0	1899	3	17	2	3	39998	60000	10	40192	40060	40264	40081	40084
60024	40245	300	0	0	14	61	39709	26	51773	10	51814	10	50000	50	5688506	1	40091	0	40101	40101	29770	3	30088	50010	20	50000	20	140000	40098	40086	1	1	30021	10	9	0	10	10	30000	10	0	0	0	1899	3	17	2	3	39953	60000	10	40096	40099	40111	40090	40084
60024	40116	300	0	0	15	61	39707	26	50027	10	50030	10	50000	50	5696628	1	40100	0	40107	40083	29767	3	30055	50010	20	50000	20	140000	40110	40089	1	1	30021	10	9	0	10	10	30000	10	0	0	0	1899	3	17	2	2	40071	60000	10	40114	40105	40108	40084	40069
60024	40068	301	0	0	24	61	39659	26	50039	10	50021	10	50000	50	5694789	1	40064	0	40113	40254	29803	3	30055	50010	20	50000	20	140000	40086	40131	1	1	30021	10	9	0	10	10	30000	10	0	0	0	1899	2	17	1	3	39960	60000	10	40141	40075	40117	40087	40081
60024	40125	300	0	0	22	726	39707	26	50033	10	50021	10	50000	50	5694789	1	40094	0	40089	40092	29788	3	30070	50010	20	50000	20	140000	40200	40116	1	1	30021	10	9	0	10	10	30000	10	0	0	0	1899	3	17	2	3	39960	60000	10	40078	40087	40117	40144	40090
60024	40095	300	0	0	23	61	39724	26	50030	10	50014	10	50000	50	5686272	1	40058	0	40086	40104	29770	3	30070	50010	20	50000	20	140000	40095	40068	1	1	30021	10	9	0	10	10	30000	10	0	0	0	1899	3	17	2	3	39963	60000	10	40114	40177	40069	40210	40099
60024	40113	302	0	0	19	61	39688	49	50023	10	50036	10	50000	50	5691546	1	40070	0	40098	40083	29876	3	30097	50010	20	50000	20	140000	40092	40071	1	1	30021	10	9	0	10	10	30000	10	0	0	0	1899	3	17	2	3	39972	60000	10	40087	40090	40105	40087	40204

Test 7: Latency 1->6

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b
  add v5.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60204	100038	749	0	0	0	944	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	99798	2	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	300	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	589	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	14300	0	0	2029	2	75	1	1	99912	1	60000	100	100039	100039	100039	100039	100039
60204	100038	750	0	6	0	61	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	0	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	750	0	0	0	212	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	12	1135	99686	26	50100	100	50000	100	50000	500	14327874	1	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	1	3	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	12	2028	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	8	90019	50100	200	50000	200	140920	100038	100038	1	1	30201	100	99	100	100	30000	100	0	3	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	750	0	0	12	2476	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	3	90019	50100	204	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	100035	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	780	99686	26	50114	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	750	0	0	0	822	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60024	100038	749	0	0	0	0	0	0	0	0	768	99686	26	50010	10	50000	10	50000	50	14327648	1	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	6	17	2	5	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	30	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	141842	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	4	0	0	1899	5	17	4	5	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	1	0	0	61	99642	26	50010	10	50000	10	50000	50	14327648	1	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	5	17	2	5	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	1	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	0	100163	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	3	1899	6	17	5	6	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	750	0	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	5	17	2	5	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	1	0	0	0	0	61	99686	26	50058	10	50000	10	50000	50	14327648	1	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	3	0	0	1899	5	17	4	3	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	573	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	3	50	4	5	99944	60000	10	100039	100039	100039	100039	100039
60024	100038	750	0	0	0	0	0	0	0	0	673	99686	26	50010	10	50000	10	50000	50	14327648	1	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	2	0	0	0	6132	1899	3	17	4	3	99798	60000	10	100039	100039	100039	100039	100089
60024	100038	749	0	0	0	0	4	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	1	100019	100134	100086	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	3	1899	3	17	2	5	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	1	0	100019	100038	100038	89696	25	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	5	51	4	3	99798	60000	10	100039	100039	100039	100039	100039

Test 8: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v1.16b, 0
  tbx v1.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v2.16b, 0
  tbx v2.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v3.16b, 0
  tbx v3.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v4.16b, 0
  tbx v4.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v5.16b, 0
  tbx v5.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v6.16b, 0
  tbx v6.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v7.16b, 0
  tbx v7.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12
  movi v12.16b, 13

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400204	80071	600	1	0	1	0	0	0	0	0	97	26	320111	100	320011	100	320032	500	3520245	0	0	80114	0	80210	80045	7	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10116	0	2	16	0	0	2	2	80042	0	400000	100	80046	80046	80046	80046	80046
400204	80045	599	1	0	1	0	0	0	0	1	32	26	320111	100	320011	100	320032	500	3520245	0	1	80026	0	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10116	0	2	16	0	0	4	3	80042	0	400000	100	80046	80046	80046	80046	80046
400204	80045	599	1	0	1	0	0	0	0	1	52	26	320111	100	320011	100	320032	500	3520245	0	0	80026	0	80045	80045	6	14	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10116	0	2	16	0	0	2	2	80042	0	400000	100	80046	80046	80046	80046	80046
400204	80045	599	1	0	1	0	0	0	0	1	31	26	320111	100	320011	100	320032	500	3520245	0	0	80026	0	80045	80045	7	14	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10116	0	2	16	0	0	2	2	80042	0	400000	100	80046	80046	80046	80046	80046
400204	80045	599	1	0	1	0	0	0	0	1	32	59	320111	100	320011	100	320032	500	3520245	0	0	80026	0	80104	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10117	0	2	16	0	0	2	2	80042	0	400000	100	80106	80046	80046	80046	80046
400204	80045	599	1	0	1	0	0	0	0	1	31	27	320111	100	320011	100	320032	500	3520245	0	0	80026	0	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	0	1	1	1	10116	0	2	16	0	0	2	2	80042	0	400000	100	80046	80046	80046	80046	80046
400204	80045	600	1	0	1	0	0	0	0	1	696	26	320111	100	320011	100	320032	500	3520245	0	0	80026	0	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10116	0	2	16	0	0	2	2	80042	0	400000	100	80046	80046	80046	80046	80046
400204	80045	600	1	0	1	0	0	0	0	1	31	26	320111	100	320011	100	320032	500	3520245	0	0	80026	0	80045	80045	7	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10116	0	2	16	0	0	2	2	80042	0	400000	100	80046	80046	80046	80046	80046
400204	80100	600	1	0	1	0	0	0	0	1	32	26	320111	100	320011	100	320032	500	3520245	0	0	80026	0	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10116	0	2	16	0	0	4	4	80042	0	400000	100	80046	80046	80046	80046	80046
400204	80045	599	1	0	1	0	0	0	0	1	32	26	320111	100	320011	100	320032	500	3520245	0	0	80026	0	80045	80045	6	14	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10117	0	2	16	0	0	2	2	80042	0	400000	100	80046	80046	80046	80046	80046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400024	80058	600	0	0	0	0	2	376	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10021	42	1	1	9	17	2	1	1	6	6	80042	15	2	400000	10	80046	80046	80046	80046	80046
400024	80045	599	0	0	0	0	1	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10021	3	1	1	5	17	2	1	1	5	6	80042	15	2	400000	10	80046	80046	80046	80046	80046
400024	80045	600	0	0	0	0	1	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10021	3	1	1	5	17	3	1	1	6	5	80042	15	2	400000	10	80046	80046	80046	80046	80046
400024	80045	600	0	0	0	0	2	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10021	3	2	1	9	17	2	2	1	8	7	80042	15	2	400000	10	80046	80046	80046	80046	80046
400024	80045	600	0	0	0	0	2	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10023	3	1	1	7	17	2	1	1	8	8	80042	15	2	400000	10	80046	80046	80046	80046	80046
400024	80045	599	0	0	0	0	2	60	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10021	3	1	1	7	17	2	1	1	6	7	80042	30	2	400000	10	80046	80046	80046	80046	80046
400024	80045	600	0	0	0	0	3	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10021	3	1	1	6	17	2	1	2	8	5	80042	15	2	400000	10	80046	80046	80046	80046	80046
400024	80045	600	0	0	0	0	1	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10021	3	1	2	6	17	2	2	1	5	7	80042	15	2	400000	10	80046	80046	80119	80046	80046
400024	80045	600	0	0	0	0	1	274	26	320010	10	320076	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10021	3	1	1	5	17	2	1	2	8	6	80042	15	2	400000	10	80046	80046	80046	80046	80046
400024	80045	599	0	0	0	0	1	55	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	1	0	0	0	0	0	10021	3	1	1	6	17	2	1	1	6	5	80042	15	2	400000	10	80046	80046	80046	80046	80046

TBX (four register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 1->6

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations