Firestorm: TBX (four register table, 8B) measurements

Code:

  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 4.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
4004	8037	60	0	0	0	103	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	0	0	73	2	16	2	2	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	61	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	0	0	73	2	16	2	2	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	61	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	0	0	73	2	16	2	2	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	9	61	7676	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	0	0	73	2	25	2	2	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	103	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	0	0	73	2	16	2	2	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	82	7687	64	4024	4024	4304	1129529	0	8090	8133	8181	6665	11	7016	4412	4492	12984	8037	8037	1	1	1001	1000	0	0	73	2	16	2	2	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	84	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	0	0	73	2	16	2	2	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	233	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	0	3	73	2	16	2	2	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	61	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	0	93	73	2	16	2	2	7796	4000	8038	8038	8038	8038	8038
4004	8037	60	0	0	0	441	7687	25	4000	4000	4000	1125680	0	8018	8037	8037	6697	3	7020	4000	4000	12000	8037	8037	1	1	1001	1000	0	0	73	2	16	2	2	7796	4000	8038	8038	8038	8038	8038

Test 2: Latency 1->1

Code:

  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	80037	600	0	0	0	0	9	0	0	536	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	3	17	1	1	79797	0	40000	100	80038	80038	80038	80038	80038
40204	80037	600	0	0	0	0	0	0	0	1610	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	17	1	1	79797	0	40000	100	80038	80038	80038	80038	80038
40204	80037	599	0	0	0	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	6	0	0	0	0	0	710	1	17	1	1	79797	0	40000	100	80038	80038	80038	80038	80038
40204	80037	599	0	0	0	0	0	0	0	631	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	2	17	1	1	79797	0	40000	100	80038	80038	80038	80038	80038
40204	80037	600	0	0	0	0	0	0	0	251	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80229	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	17	1	1	79797	0	40000	100	80038	80038	80038	80038	80038
40204	80037	600	0	0	0	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	12	0	0	0	710	1	17	1	1	79797	0	40000	100	80038	80038	80038	80038	80038
40204	80037	599	0	0	0	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	17	1	1	79797	0	40000	100	80038	80038	80038	80038	80038
40204	80037	599	0	0	0	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	2	17	1	1	79797	0	40000	100	80038	80038	80038	80038	80038
40204	80037	599	0	0	0	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	17	1	1	79797	0	40000	100	80038	80038	80038	80038	80038
40204	80037	600	0	0	0	0	0	0	0	61	79687	25	40100	100	40000	100	40000	500	11457680	1	80018	80037	80037	69697	3	70019	40100	200	40000	200	120000	80037	80228	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	17	1	1	79797	0	40000	100	80038	80038	80038	80038	80038

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	80037	599	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	0	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	649	1	17	0	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	600	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	1	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	1	3	649	3	17	0	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	108	79687	25	40010	10	40000	10	40000	50	11457680	1	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	649	3	17	0	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	0	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80228	1	1	10021	10	9	10	10	10000	10	0	0	0	669	2	17	0	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	0	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	649	3	17	0	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	124	79687	25	40010	10	40000	10	40000	50	11457680	1	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	649	2	17	0	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	1	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	649	3	17	0	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	0	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	649	2	17	0	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	599	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	1	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80230	80037	1	1	10021	10	9	10	10	10000	10	0	0	2015	649	4	17	0	1	79797	40000	10	80038	80038	80038	80038	80038
40024	80037	600	0	0	61	79687	25	40010	10	40000	10	40000	50	11457680	0	80018	80037	80037	69697	0	3	70019	40010	20	40000	20	120000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	649	2	17	0	1	79797	40000	10	80038	80038	80038	80038	80038

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	9	0	726	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50112	120	50216	120	50152	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	750	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100089	100039	100039	100039	100039
60204	100038	750	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	750	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	0	100019	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60024	100038	749	0	1	0	0	0	0	0	24	0	0	61	99686	26	50010	10	50012	10	50000	50	14327648	0	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100087	100038	1	1	30021	10	9	10	10	30000	10	0	0	2	0	0	0	0	1899	0	8	17	0	5	6	99798	0	0	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	1	0	0	0	189	0	0	103	99686	26	50010	10	50000	10	50000	50	14327648	0	1	100055	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1899	0	6	17	0	4	6	99798	0	0	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1899	0	6	17	0	5	6	99798	0	0	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	1	0	0	0	61	99686	26	50010	10	50012	10	50000	50	14327648	0	1	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1899	0	6	17	0	4	5	99798	0	0	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	1	100019	100038	100038	89696	9	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	3	0	1917	0	5	17	0	6	9	99798	0	0	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	165	0	0	191	99686	26	50010	10	50000	10	50000	50	14327648	0	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1899	0	4	17	0	7	6	99798	0	0	60000	10	100039	100039	100039	100039	100039
60024	100038	750	0	0	0	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	1	0	3	0	1899	0	6	17	0	4	6	99798	0	0	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	2	0	0	0	0	0	1899	0	6	17	0	5	6	99798	0	0	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	0	0	0	0	12	0	0	536	99686	26	50010	10	50000	10	50000	50	14327648	0	0	100019	100038	100038	89696	3	90019	50010	20	50165	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	2	0	0	0	0	1899	0	6	17	0	4	6	99798	0	0	60000	10	100039	100039	100039	100039	100039
60024	100038	750	0	0	0	0	0	0	0	0	0	0	189	99686	26	50010	10	50000	10	50000	50	14327648	0	1	100055	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	3	2	1922	0	7	17	0	5	4	99798	0	0	60000	10	100039	100039	100039	100039	100039

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60204	80040	599	0	0	2	0	61	79682	26	50100	100	50000	100	50000	500	11447447	1	80021	80040	80040	69718	7	6	70017	50100	200	50009	200	140026	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	1	1	1	1917	0	16	0	0	79890	0	60000	100	80041	80044	80044	80041	80041
60204	80040	599	0	0	1	0	61	79682	26	50101	100	50001	100	50000	500	11447447	1	80021	80040	80040	69718	0	6	70020	50100	200	50009	200	140026	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	1	1	1	1916	0	16	0	0	79845	0	60000	100	80041	80044	80041	80044	80041
60204	80040	599	0	0	1	0	61	79662	26	50101	100	50000	100	50000	500	11447447	1	80021	80095	80040	69718	0	6	70017	50100	200	50009	200	140026	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	1	1	1	1916	0	16	0	0	79836	0	60000	100	80041	80041	80044	80041	80041
60204	80040	599	0	0	0	0	2862	79682	26	50101	100	50001	100	50000	500	11447447	1	80021	80040	80040	69718	0	7	70016	50100	200	50009	200	140026	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	1	1	1	1916	0	16	0	0	79835	0	60000	100	80041	80041	80041	80041	80041
60204	80040	600	0	0	0	0	61	79696	26	50100	100	50001	100	50000	500	11447447	1	80021	80040	80040	69718	0	6	70017	50100	200	50009	200	140026	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	1	1	1	1916	0	16	0	0	79835	0	60000	100	80323	80041	80041	80041	80041
60204	80040	599	0	0	0	0	61	79682	26	50103	100	50000	100	50000	500	11447447	1	80021	80040	80040	69718	0	6	70017	50100	200	50009	200	140026	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	1	1	1	1917	0	16	0	0	79835	0	60000	100	80041	80041	80041	80041	80041
60204	80043	600	0	0	1	0	61	79682	26	50100	100	50000	100	50000	500	11447447	1	80021	80040	80040	69718	0	6	70017	50100	200	50009	200	140026	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	1	1	1	1916	0	16	0	0	79836	0	60000	100	80041	80041	80041	80041	80041
60204	80040	599	0	0	0	0	61	79682	26	50100	100	50000	100	50186	500	11447447	1	80021	80040	80040	69718	0	6	70017	50100	200	50009	200	140026	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	1	1	1	1916	0	16	0	0	79835	0	60000	100	80044	80041	80041	80041	80096
60204	80092	600	0	0	0	0	61	79682	26	50101	100	50001	100	50000	500	11447447	1	80021	80040	80040	69718	0	6	70017	50100	200	50009	200	140026	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	1	1	1	1917	0	16	0	0	79835	0	60000	100	80041	80041	80041	80041	80041
60204	80040	599	0	0	0	0	61	79682	26	50100	100	50000	100	50000	500	11447447	1	80021	80040	80040	69700	0	7	70016	50100	200	50009	200	140026	80040	80040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	1	1	1	1916	0	16	0	0	79836	0	60000	100	80041	80041	80041	80041	80041

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60024	80040	600	0	0	0	2	61	79682	26	50010	10	50000	10	50000	50	11447447	0	0	80021	80040	80040	69704	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	90	0	1899	2	17	7	4	79894	0	60000	10	80041	80041	80041	80094	80041
60024	80040	599	0	0	0	2	61	79682	26	50010	10	50053	10	50000	50	11447447	0	0	80021	80040	80040	69656	3	70021	50199	20	50000	20	140000	80198	80251	2	1	30021	10	9	10	10	30000	10	0	0	1899	4	17	4	5	79821	0	60000	10	80041	80044	80041	80041	80041
60024	80040	599	0	0	0	1	61	79682	26	50010	10	50000	10	50000	50	11447447	0	0	80021	80040	80040	69707	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	72	0	1899	2	17	3	4	79821	0	60000	10	80041	80041	80041	80041	80041
60024	80040	600	0	0	0	2	61	79682	26	50011	10	50000	10	50000	50	11447447	0	0	80021	80040	80040	69704	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	74	0	1899	4	17	3	4	79821	0	60000	10	80041	80041	80041	80041	80041
60024	80040	600	0	0	132	0	61	79685	26	50011	10	50000	10	50000	50	11447447	0	0	80021	80040	80040	69704	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30022	10	9	10	10	30000	10	36	0	1899	2	17	1	5	79821	0	60000	10	80041	80041	80041	80041	80041
60024	80040	599	0	0	0	1	61	79682	26	50011	10	50000	10	50000	50	11447882	0	0	80021	80040	80040	69704	3	70024	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	68	0	1899	4	17	3	5	79821	0	60000	10	80041	80041	80044	80041	80044
60024	80040	599	0	0	0	0	61	79682	49	50010	10	50001	10	50000	50	11447447	0	1	80021	80043	80040	69704	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	75	0	1899	4	17	2	4	79821	0	60000	10	80041	80041	80041	80041	80041
60024	80040	599	0	0	0	0	61	79682	26	50010	10	50000	10	50000	50	11447447	0	1	80021	80040	80040	69704	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	85	0	1899	3	17	3	4	79821	0	60000	10	80041	80041	80041	80041	80041
60024	80040	599	0	0	0	0	61	79682	26	50011	10	50000	10	50000	50	11447447	0	1	80021	80040	80040	69704	3	70021	50010	20	50000	20	140000	80040	80040	1	1	30021	10	9	10	10	30000	10	72	0	1899	4	17	2	5	79821	0	60000	10	80041	80041	80041	80041	80041
60024	80043	599	0	0	0	0	61	79682	26	50010	10	50000	10	50000	50	11447447	0	1	80021	80040	80040	69704	3	70021	50010	20	50000	20	140000	80043	80040	1	1	30021	10	9	10	10	30000	10	0	0	1899	3	17	2	4	79821	0	60000	10	80044	80041	80041	80041	80041

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0042

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60204	60042	450	0	0	0	0	0	0	0	61	59703	26	50100	100	50001	100	50000	500	8564469	1	60023	0	60048	60054	49727	3	50023	50100	200	50000	200	140000	60042	60054	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59853	60000	100	60055	60043	60055	60043	60055
60204	60054	450	0	0	0	0	0	0	0	82	59686	26	50104	100	50004	100	50000	500	8564469	1	60023	0	60042	60054	49727	3	50035	50100	200	50000	200	140000	60054	60042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59853	60000	100	60043	60043	60049	60049	60043
60204	60042	449	0	0	0	255	132	2	0	61	59703	26	50101	100	50001	100	50000	500	8565351	1	60023	0	60048	60042	49715	3	50035	50100	200	50000	200	140000	60054	60042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59859	60000	100	60043	60043	60049	60055	60043
60204	60042	450	0	0	0	0	0	0	0	61	59686	26	50104	100	50004	100	50000	500	8564497	0	60023	0	60048	60048	49715	3	50029	50100	200	50000	200	140000	60054	60042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59853	60000	100	60043	60049	60043	60043	60055
60204	60042	450	0	0	0	0	0	2	0	61	59679	26	50100	100	50000	100	50000	500	8564469	1	60029	0	60048	60054	49727	3	50035	50100	200	50000	200	140000	60054	60042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59853	60000	100	60055	60049	60043	60049	60043
60204	60054	450	0	0	0	0	0	2	0	61	59679	26	50104	100	50004	100	50000	500	8564469	1	60023	0	60096	60042	49721	3	50035	50100	200	50000	200	140000	60054	60042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59859	60000	100	60055	60043	60055	60043	60055
60204	60054	449	0	0	0	0	0	2	0	726	59679	26	50101	100	50001	100	50000	500	8565609	1	60035	0	60054	60042	49715	3	50023	50100	200	50000	200	140000	60042	60054	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59865	60000	100	60055	60043	60043	60043	60049
60204	60054	450	0	0	0	0	0	2	0	61	59679	26	50100	100	50000	100	50000	500	8565609	0	60035	3	60042	60042	49721	3	50023	50100	200	50000	200	140000	60042	60054	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59865	60000	100	60043	60055	60043	60055	60043
60204	60042	450	0	0	0	0	0	4	0	61	59686	26	50100	100	50001	100	50000	500	8564469	1	60023	0	60042	60054	49727	3	50035	50100	200	50000	200	140000	60042	60042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59853	60000	100	60043	60049	60049	60043	60043
60204	60042	450	0	0	0	0	0	3	0	61	59679	26	50100	100	50000	100	50000	500	8565609	1	60035	0	60054	60042	49715	3	50023	50100	200	50000	200	140000	60042	60054	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	17	1	1	59853	60000	100	60055	60043	60055	60043	60055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0042

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60024	60042	449	0	0	0	0	0	0	1407	59686	26	50013	10	50002	10	50000	50	8564469	0	1	60035	0	60042	60048	49704	3	50023	50010	20	50000	20	140000	60042	60048	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	1	17	0	0	1	59865	0	0	0	60000	10	60043	60049	60049	60043	60049
60024	60042	450	0	0	1	9	0	4	637	59679	26	50010	10	50000	10	50000	50	8565609	0	1	60023	0	60054	60054	49715	3	50023	50010	20	50000	20	140000	60042	60054	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	1	17	0	0	1	59853	0	0	0	60000	10	60049	60043	60043	60043	60055
60024	60054	449	0	0	0	0	0	0	2148	59679	26	50011	10	50000	10	50000	50	8565351	0	1	60023	0	60042	60054	49727	3	50035	50010	20	50000	20	140000	60054	60042	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	1	17	0	0	1	59853	0	0	0	60000	10	60055	60043	60055	60043	60055
60024	60054	450	0	0	0	0	0	0	1841	59703	26	50014	10	50004	10	50000	50	8564469	0	1	60023	0	60042	60054	49727	3	50035	50010	20	50000	20	140000	60042	60048	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	4	17	0	0	1	59853	0	0	0	60000	10	60043	60055	60043	60055	60043
60024	60042	450	0	0	0	0	0	4	1986	59679	26	50010	10	50002	10	50000	50	8565351	0	0	60023	0	60042	60048	49721	3	50023	50010	20	50000	20	140000	60042	60054	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	1	17	0	0	1	59865	0	0	0	60000	10	60055	60043	60055	60043	60055
60024	60054	449	0	0	0	0	0	0	1909	59679	26	50010	10	50000	10	50000	50	8565609	0	0	60035	0	60054	60042	49715	30	50023	50010	20	50000	20	140000	60048	60048	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	1	17	0	0	1	59859	0	0	0	60000	10	60049	60049	60049	60043	60043
60024	60042	449	0	0	0	0	0	0	1951	59703	26	50010	10	50002	10	50000	50	8564469	0	1	60023	0	60042	60054	49727	3	50023	50010	20	50000	20	140000	60054	60042	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	1	17	0	0	1	59865	0	0	0	60000	10	60043	60055	60043	60055	60043
60024	60042	450	0	0	0	0	0	4	61	59641	26	50010	10	50002	10	50000	50	8565609	1	1	60035	0	60054	60042	49715	3	50029	50010	20	50000	20	140000	60042	60048	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	1	17	0	0	1	59853	0	0	0	60000	10	60055	60046	60055	60043	60055
60024	60054	449	0	0	0	0	0	4	655	59686	26	50014	10	50004	10	50000	50	8564469	0	0	60023	0	60042	60054	49727	3	50035	50010	20	50000	20	140000	60054	60042	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	1	17	0	0	1	59853	0	0	0	60000	10	60055	60043	60043	60055	60043
60024	60042	450	0	0	0	0	0	2	256	59686	26	50014	10	50004	10	50000	50	8564469	0	0	60023	0	60042	60054	49727	3	50035	50010	20	50000	20	140000	60054	60042	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	2	17	0	0	1	59853	0	0	0	60000	10	60043	60055	60043	60043	60043

Test 6: Latency 1->5

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b
  add v4.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0098

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60204	40065	300	0	0	0	0	0	1790	61	39675	26	51902	100	50004	100	50000	500	5689675	0	40088	40218	40065	29765	3	30061	50100	200	50000	200	140000	40086	40122	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	39927	0	60000	100	40111	40081	40087	40132	40105
60204	40110	300	0	0	0	0	0	17	61	39725	26	51824	100	51718	100	50000	500	5688421	0	40049	40122	40125	29797	3	30073	50100	200	50000	200	140000	40104	40068	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	39957	0	60000	100	40123	40069	40081	40105	40303
60204	40089	300	0	0	0	0	0	15	61	39708	26	50115	100	50023	100	50000	500	5692701	0	40061	40083	40065	29776	3	30097	50100	200	50000	200	140000	40113	40134	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	39980	0	60000	100	40114	40102	40102	40108	40105
60204	40068	300	0	0	0	0	0	15	103	39718	26	50132	100	50024	100	50000	500	5689297	0	40079	40080	40098	29761	3	30088	50100	200	50000	200	140000	40086	40086	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	40295	0	60000	100	40111	40111	40102	40111	40114
60204	40098	300	0	0	0	0	0	1790	89	39705	26	50116	100	50020	100	50000	500	5691875	0	40064	40218	40089	29788	3	30070	50100	200	50000	200	140000	40062	40098	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	39936	0	60000	100	40084	40216	40147	40183	40093
60204	40206	300	0	0	0	0	0	15	61	39694	26	50114	100	50034	100	50000	500	5686216	0	40058	40098	40098	29785	3	30085	50100	200	50000	200	140000	40092	40266	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	39948	0	60000	100	40084	40099	40243	40108	40108
60204	40101	301	0	0	0	0	0	22	61	39690	26	50121	100	50019	100	50000	500	5711155	0	40088	40227	40095	29800	3	30067	50100	200	50000	200	140000	40086	40113	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	39963	0	60000	100	40090	40129	40060	40081	40126
60204	40236	300	0	0	0	0	0	1764	61	39703	26	50116	100	50021	100	50000	500	5689714	0	40073	40101	40110	29758	3	30067	50100	200	50000	200	140000	40086	40083	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	0	17	1	1	39987	0	60000	100	40093	40084	40102	40177	40129
60204	40080	300	0	0	0	0	0	15	61	39715	26	50116	100	50007	100	50000	500	5687501	0	40262	40119	40173	29783	3	30088	50100	200	50000	200	140000	40248	40116	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	40102	0	60000	100	40222	40233	40336	40102	40093
60204	40215	301	0	0	0	0	0	24	61	39703	26	50126	100	51851	100	50000	500	5688421	0	40049	40104	40104	29779	3	30160	50100	200	50000	200	140000	40083	40056	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1910	1	17	1	1	39948	0	60000	100	40087	40063	40099	40087	40108

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0095

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60024	40077	300	0	16	900	39698	26	50025	10	50025	10	50000	50	5688665	1	40079	40125	40113	29797	0	3	30082	50010	20	50000	20	140000	40077	40071	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	0	0	0	6	17	0	0	0	5	6	39951	0	0	60000	10	40096	40099	40081	40093	40090
60024	40077	300	0	1692	189	39678	26	50041	10	50011	10	50000	50	5688116	1	40094	40101	40080	29800	0	3	30064	50010	20	50000	20	140000	40176	40254	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	0	0	0	6	17	0	0	0	3	6	39969	0	0	60000	10	40123	40087	40120	40099	40072
60024	40080	300	0	1751	61	39728	26	50038	10	50019	10	50000	50	5691524	0	40082	40071	40089	29803	0	3	30085	50010	20	50000	20	140000	40095	40119	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	0	0	0	12	17	0	0	0	6	7	40128	0	0	60000	10	40123	40108	40126	40075	40087
60024	40095	301	0	23	61	39689	26	50032	10	50013	10	50000	50	5689434	0	40091	40119	40083	29782	0	3	30070	50010	20	50000	20	140000	40107	40074	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	0	0	0	6	17	0	0	0	6	7	39960	0	0	60000	10	40108	40117	40126	40096	40255
60024	40068	301	0	16	726	39856	26	50035	10	50027	10	50000	50	5709615	1	40100	40104	40131	29767	0	3	30064	50010	20	50000	20	140000	40077	40080	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	0	0	0	7	17	0	0	0	3	7	39951	0	0	60000	10	40144	40108	40108	40084	40072
60024	40080	301	0	31	103	39859	26	51827	10	50024	10	50000	50	5707621	0	40088	40095	40104	29770	0	3	30076	50010	20	50000	20	140000	40086	40086	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	0	0	0	7	17	0	0	0	7	8	39954	0	0	60000	10	40081	40075	40111	40090	40180
60024	40107	300	0	21	61	39721	26	50032	10	50014	10	50000	50	5688558	0	40076	40083	40110	29785	0	3	30184	50010	20	50000	20	140000	40116	40101	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	0	0	0	9	17	0	0	0	7	5	39948	0	0	60000	10	40207	40078	40114	40087	40225
60024	40080	300	0	18	61	39749	26	50027	10	50020	10	50000	50	5685325	0	40112	40254	40113	29782	0	3	30091	50010	20	50000	20	140000	40104	40098	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	0	0	0	6	17	0	0	0	5	6	39963	0	0	60000	10	40072	40084	40216	40078	40087
60024	40119	301	0	17	61	39736	26	50026	10	50019	10	50000	50	5690113	0	40076	40107	40104	29767	0	3	30100	50010	20	50000	20	140000	40113	40113	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	0	0	0	7	17	0	0	0	5	7	39975	0	0	60000	10	40069	40096	40246	40179	40093
60024	40101	300	0	19	61	39687	26	50031	10	51789	10	50000	50	5692228	1	40073	40110	40101	29764	0	3	30079	50010	20	50000	20	140000	40110	40203	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1899	0	0	0	7	17	0	0	0	6	6	39957	0	0	60000	10	40111	40192	40087	40135	40087

Test 7: Latency 1->6

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b
  add v5.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60204	100038	750	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	0	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	726	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	0	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	1	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	0	100038	100038	89699	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	0	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	0	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	1135	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	0	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	0	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	0	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	749	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	0	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039
60204	100038	750	0	0	0	0	0	0	61	99686	26	50100	100	50000	100	50000	500	14327648	1	100019	3	100038	100038	89696	3	90019	50100	200	50000	200	140000	100038	100038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	17	1	1	99798	0	60000	100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60024	100038	749	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	0	4	17	3	2	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	536	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	0	4	17	3	4	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	0	4	17	3	4	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140460	100038	100233	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	0	2	17	3	4	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	750	0	0	0	726	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140488	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	0	4	17	3	2	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	0	2	17	3	2	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	749	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	0	4	17	1	4	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	750	0	6	0	726	99686	26	50010	10	50000	10	50000	50	14327648	1	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	0	4	17	1	4	99798	60000	10	100039	100091	100039	100039	100039
60024	100038	750	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	0	2	17	3	4	99798	60000	10	100039	100039	100039	100039	100039
60024	100038	750	0	0	0	61	99686	26	50010	10	50000	10	50000	50	14327648	0	100019	100038	100038	89696	3	90019	50010	20	50000	20	140000	100038	100038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1899	0	4	17	3	2	99798	60000	10	100039	100039	100039	100039	100039

Test 8: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v1.16b, 0
  tbx v1.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v2.16b, 0
  tbx v2.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v3.16b, 0
  tbx v3.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v4.16b, 0
  tbx v4.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v5.16b, 0
  tbx v5.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v6.16b, 0
  tbx v6.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v7.16b, 0
  tbx v7.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12
  movi v12.16b, 13

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400204	80058	600	0	0	0	0	0	150	0	32	26	320111	100	320011	100	320032	500	3520245	1	80026	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10116	1	16	1	1	80042	400000	100	80046	80046	80046	80046	80046
400204	80045	600	0	0	0	0	0	393	0	31	26	320111	100	320011	100	320032	500	3520245	1	80026	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10116	1	16	1	1	80042	400000	100	80046	80046	80046	80046	80046
400204	80045	600	0	0	0	0	0	78	0	32	26	320111	100	320011	100	320032	500	3520245	0	80026	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10117	1	16	1	1	80042	400000	100	80046	80046	80046	80046	80046
400204	80045	599	0	0	0	0	0	366	0	31	26	320111	100	320011	100	320032	500	3520245	1	80026	80045	80045	6	14	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10116	1	16	1	1	80042	400000	100	80046	80046	80046	80046	80046
400205	80045	600	0	0	0	0	0	45	0	32	26	320111	100	320011	100	320032	500	3520245	1	80070	80155	80045	15	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	1	4	498	0	1	1	1	10116	1	16	1	1	80042	400000	100	80046	80046	80046	80046	80046
400204	80045	599	0	0	0	0	0	45	0	222	27	320111	100	320011	100	320032	500	3520245	1	80026	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10116	1	16	1	1	80042	400000	100	80046	80046	80046	80046	80046
400204	80156	600	0	1	0	1	0	132	0	739	27	320111	100	320011	100	320032	500	3520245	0	80026	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10117	1	16	1	1	80042	400000	100	80046	80046	80046	80046	80046
400204	80045	599	0	0	0	0	0	108	0	32	26	320111	100	320011	100	320032	500	3520245	1	80026	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	4	1	1	1	10117	1	16	1	1	80042	400000	100	80046	80046	80046	80046	80046
400204	80045	600	0	0	0	0	0	513	0	32	27	320111	100	320011	100	320032	500	3520245	1	80026	80045	80045	6	15	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10116	1	16	1	1	80042	400000	100	80046	80046	80046	80046	80046
400204	80045	599	0	0	0	0	0	288	0	31	26	320111	100	320011	100	320032	500	3520245	1	80026	80045	80045	6	14	320132	200	320032	200	960096	80045	80045	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10116	1	16	1	1	80042	400000	100	80046	80046	80046	80046	80046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80058	600	1	0	0	0	0	49	26	320010	10	320000	10	320000	50	3520000	0	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	10026	3	4	2	1	50	17	1	2	1	40	39	80042	16	6	400000	10	80046	80046	80046	80101	80046
400024	80045	599	1	0	0	0	9	55	26	320010	10	320000	10	320000	50	3520000	1	1	80026	3	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	10025	6	3	2	0	41	17	1	2	1	25	41	80042	31	3	400000	10	80046	80046	80046	80046	80046
400024	80045	599	0	0	0	0	0	241	26	320010	10	320000	10	320000	50	3520000	0	0	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	10023	3	1	1	0	62	17	1	2	1	38	38	80042	16	3	400000	10	80046	80046	80046	80046	80046
400024	80045	600	0	0	0	0	0	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	10023	6	1	1	0	26	17	3	1	1	41	23	80042	16	3	400000	10	80046	80046	80046	80046	80046
400024	80045	600	0	0	0	0	0	49	26	320010	10	320000	10	320000	50	3520000	1	0	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	10023	6	2	1	0	42	17	1	1	1	41	41	80042	16	3	400000	10	80046	80046	80046	80046	80046
400024	80045	599	0	0	0	0	0	49	26	320010	10	320000	10	320000	50	3520000	0	1	80026	0	80045	80045	3	26	320010	20	320000	20	960096	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	10023	3	1	1	0	27	17	1	1	1	41	28	80042	21	3	400000	10	80046	80046	80046	80102	80105
400024	80045	599	0	0	0	0	0	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	10025	3	1	1	0	42	17	1	1	1	29	42	80042	21	3	400000	10	80046	80046	80046	80046	80046
400024	80045	600	0	0	0	0	0	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	10023	3	1	1	0	43	17	1	1	1	26	41	80042	21	3	400000	10	80046	80046	80046	80046	80046
400024	80045	600	0	0	0	0	0	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	10023	3	1	1	0	41	17	1	1	1	44	45	80042	21	3	400000	10	80046	80046	80046	80046	80046
400024	80045	600	0	0	0	0	0	49	26	320010	10	320000	10	320000	50	3520000	1	1	80026	0	80045	80045	3	26	320010	20	320000	20	960000	80045	80045	1	1	160021	10	9	10	10	160000	10	0	0	10021	3	1	1	0	41	19	1	1	1	43	43	80042	21	3	400000	10	80107	80046	80046	80046	80046

TBX (four register table, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 1->6

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations