Firestorm: TBX (single register table, 16B) measurements

Code:

  tbx v0.16b, { v1.16b }, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	84	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1032	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	701	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	12	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	2004	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  tbx v0.16b, { v1.16b }, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	69	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	9	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	204	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	3	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	346	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	423	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	18	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	21	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	18	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	3	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	24	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	12	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	9	346	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	3	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30486	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  tbx v0.16b, { v0.16b }, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	18	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2848963	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1975	4	754	1	46	1	2	19791	0	10000	100	20038	20038	20086	20038	20133
10204	20133	151	1	1	1	156	104	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	8	18762	10429	204	10166	204	30501	20085	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	1	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	1	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20083
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	51	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18803	10774	22	10671	20	32487	20228	20272	5	1	10021	10	9	10	10	10000	10	0	2	2	1	0	9850	2	725	5	77	11	5	19968	2	10000	10	20276	20273	20276	20226	20266
10024	20131	151	0	1	0	4	5	684	352	6	2532	19632	116	10059	11	10060	11	10760	50	2852812	1	20162	20274	20274	18459	26	18855	10772	20	10992	22	31989	20261	20262	6	1	10021	10	9	10	10	10000	10	0	0	0	1	2	9703	0	731	4	57	6	3	19785	6	10000	10	20275	20274	20311	20228	20169

Test 4: Latency 1->3

Code:

  tbx v0.16b, { v1.16b }, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	5	0	12	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	75	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	3	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	53	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	637	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	39	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10012	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	103	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20083	20133	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	0	0	0	0	640	2	16	2	2	19823	0	10000	10	20085	20038	20038	20038	20085
10024	20037	150	0	0	0	0	0	82	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20084	20037	18444	3	18779	10010	20	10000	20	30000	20037	20084	2	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	726	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	12	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20021	20037	20181	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	3	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.16b, { v8.16b }, v9.16b
  movi v1.16b, 0
  tbx v1.16b, { v8.16b }, v9.16b
  movi v2.16b, 0
  tbx v2.16b, { v8.16b }, v9.16b
  movi v3.16b, 0
  tbx v3.16b, { v8.16b }, v9.16b
  movi v4.16b, 0
  tbx v4.16b, { v8.16b }, v9.16b
  movi v5.16b, 0
  tbx v5.16b, { v8.16b }, v9.16b
  movi v6.16b, 0
  tbx v6.16b, { v8.16b }, v9.16b
  movi v7.16b, 0
  tbx v7.16b, { v8.16b }, v9.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	1	0	0	0	809	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	124	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	59	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	155	0	0	0	0	182	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	206	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10136	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	185	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	151	0	0	0	0	654	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	1	0	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	151	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20073	150	519	27	80012	12	80000	12	80000	62	640000	0	1	5	20031	20059	20059	3	21	80012	20	80000	20	240000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10030	11	4	1	10	25	2	1	1	7	11	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	99	10030	8	2	1	11	25	2	1	1	11	9	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	151	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	6	10030	8	3	1	9	25	2	1	1	7	11	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20286	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	96	10030	8	3	1	7	25	2	1	1	11	11	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	44	27	80012	12	80000	12	80101	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	1	9	10030	8	3	1	11	25	2	1	1	11	7	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	151	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	6	10030	8	3	1	11	25	2	1	1	11	7	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	52	6	10030	8	2	1	11	25	2	1	1	11	11	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	5	0	10030	8	3	1	11	25	2	1	1	11	11	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	44	27	80104	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	129	10030	8	2	1	11	25	2	1	1	7	11	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	1	6	10034	8	3	1	7	25	2	1	1	11	11	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051

Test 6: throughput

Count: 16

Code:

  tbx v0.16b, { v16.16b }, v17.16b
  tbx v1.16b, { v16.16b }, v17.16b
  tbx v2.16b, { v16.16b }, v17.16b
  tbx v3.16b, { v16.16b }, v17.16b
  tbx v4.16b, { v16.16b }, v17.16b
  tbx v5.16b, { v16.16b }, v17.16b
  tbx v6.16b, { v16.16b }, v17.16b
  tbx v7.16b, { v16.16b }, v17.16b
  tbx v8.16b, { v16.16b }, v17.16b
  tbx v9.16b, { v16.16b }, v17.16b
  tbx v10.16b, { v16.16b }, v17.16b
  tbx v11.16b, { v16.16b }, v17.16b
  tbx v12.16b, { v16.16b }, v17.16b
  tbx v13.16b, { v16.16b }, v17.16b
  tbx v14.16b, { v16.16b }, v17.16b
  tbx v15.16b, { v16.16b }, v17.16b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2504

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40070	300	0	338	41	73	25	160206	100	160001	100	160000	500	1320000	0	40019	40038	40124	19976	0	3	19996	160100	200	160000	200	480000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	6	16	3	3	40121	160000	100	40137	40063	40108	40039	40063
160204	40078	300	0	144	40	6	25	160119	100	160001	102	160096	500	5482191	0	40020	40073	40039	19981	0	3	19996	160100	200	160000	200	480000	40038	40075	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	5	16	3	3	40035	160000	100	40066	40040	40056	40102	40063
160204	40087	300	0	0	40	6	25	160100	100	160000	100	160000	500	4437926	0	40019	40065	40039	19974	0	3	20015	160100	200	160000	200	480000	40055	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	7	16	3	3	40062	160000	100	40079	40058	40066	40040	40039
160204	40038	300	0	106	61	149	25	160100	100	160000	100	160000	500	1319998	0	40082	40112	40038	19973	0	3	19996	160100	200	160000	200	480000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	6	16	3	2	40035	160000	100	40040	40066	40039	40210	40039
160204	40062	300	0	0	40	149	25	160100	100	160001	100	160000	500	5518691	0	40019	40038	40112	19973	0	3	19996	160100	200	160000	200	480000	40063	40065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	4	16	3	3	40035	160000	100	40039	40113	40039	40040	40064
160204	40039	300	0	106	40	197	25	160199	100	160001	100	160000	500	1280000	0	40019	40038	40112	19976	0	3	20070	160100	200	160000	200	480000	40055	40101	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	4	16	3	3	40059	160000	100	40039	40039	40039	40039	40079
160204	40038	301	0	0	41	232	25	160136	100	160000	100	160000	500	1280000	0	40019	40057	40112	19973	0	3	19996	160100	200	160000	200	480000	40065	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	6	16	3	3	40035	160000	100	40113	40039	40113	40039	40063
160204	40062	300	0	0	40	10	25	160101	100	160000	100	160000	500	5518618	0	40020	40039	40038	19973	0	3	19996	160100	200	160000	200	480000	40038	40057	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	7	16	3	3	40059	160000	100	40039	40153	40039	40145	40039
160204	40038	300	0	0	61	122	25	160100	100	160000	100	160000	500	4728951	0	40020	40038	40065	19975	0	3	19996	160100	200	160000	200	480000	40057	40101	1	1	160201	100	99	100	100	160000	100	0	1	3	0	0	10110	7	16	3	3	40035	160000	100	40039	40056	40220	40076	40066
160204	40112	300	0	106	61	0	25	160136	100	160000	100	160000	500	1319998	0	40133	40289	40289	20014	0	3	19996	160100	200	160000	200	480000	40038	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	5	16	3	3	40035	160000	100	40057	40066	40039	40040	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40048	300	1	1	0	78	1	79	270	25	160159	10	160000	10	160000	50	1280000	1	1	40019	40095	40038	20084	0	3	20018	160010	20	160000	20	480000	40145	40038	2	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	3	1	1	1	22	16	2	1	11	15	15	40035	0	15	6	160000	10	40039	40039	40039	40039	40039
160024	40038	300	1	1	0	0	1	57	0	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	3	1	1	1	15	16	2	1	17	14	15	40035	0	15	5	160000	10	40039	40039	40096	40039	40078
160024	40038	300	0	1	0	0	1	79	111	25	160010	10	160000	10	160000	50	1319997	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40153	40095	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	3	1	1	0	17	16	2	1	11	15	15	40035	0	15	5	160000	10	40096	40039	40039	40096	40096
160024	40100	300	1	1	21	0	1	682	111	25	160010	10	160078	10	160000	50	1280000	1	1	40019	40038	40153	20026	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	3	1	1	1	16	16	2	1	11	15	15	40092	0	15	10	160000	10	40039	40039	40039	40039	40039
160024	40038	300	1	1	0	78	1	85	111	25	160010	10	160000	10	160000	50	1280000	1	1	40076	40038	40038	19996	0	3	20075	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	3	1	1	1	17	16	2	1	11	17	18	40035	0	15	5	160000	10	40039	40039	40039	40039	40039
160024	40095	300	1	1	24	0	1	57	0	25	160010	10	160149	10	160000	50	5526046	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40099	1	1	160021	10	9	10	10	160000	10	1	0	3	0	0	10023	3	1	1	1	16	16	2	1	11	15	16	40035	0	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	301	1	1	0	0	1	51	0	25	160011	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40218	40095	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	3	1	1	1	11	16	2	1	11	15	15	40035	0	15	5	160000	10	40096	40039	40039	40039	40039
160024	40038	300	0	0	0	78	0	45	111	25	160010	10	160000	10	160000	50	5519418	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40095	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	0	15	16	2	1	11	13	8	40035	0	15	5	160000	10	40039	40154	40096	40039	40039
160025	40038	300	0	0	0	52	0	45	111	25	160010	10	160000	10	160000	50	5519418	1	1	40019	40038	40153	20026	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	0	16	16	2	1	12	14	15	40092	0	15	5	160000	10	40096	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	0	25	160010	10	160078	10	160000	50	1280000	1	1	40019	40095	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	0	17	16	2	1	10	15	16	40035	0	15	5	160000	10	40039	40039	40096	40039	40039

TBX (single register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations