Firestorm: TBX (single register table, 8B) measurements

Code:

  tbx v0.8b, { v1.16b }, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2022	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1	3	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	24	82	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	24	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	9	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  tbx v0.8b, { v1.16b }, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	149	0	0	0	0	0	0	0	124	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	0	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	139	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	0	2	16	2	2	19862	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	251	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20084	18424	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10202	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	0	2	16	3	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	107	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	0	2	16	2	3	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	1	0	5980	0	805	0	3	48	3	4	19897	6	10000	100	20038	20038	20038	20038	20038
10204	20276	150	1	1	0	2	672	352	0	2471	19643	102	10172	114	10060	112	10608	593	2852812	0	20198	20277	20276	18437	24	18837	10876	218	10828	216	32487	20276	20275	5	1	10201	100	99	100	100	10000	100	4	0	2	0	1	2	9603	4	806	0	2	56	2	2	19973	6	10000	100	20276	20277	20278	20280	20273
10204	20229	152	1	0	4	5	792	352	0	2422	19632	122	10175	118	10060	116	10760	598	2852698	0	20162	20275	20275	18436	26	18819	10765	214	10831	214	32481	20274	20276	5	1	10201	100	99	100	100	10000	100	0	2	2	1	1	0	9783	0	800	0	3	56	4	3	19989	7	10000	100	20277	20266	20276	20280	20276
10204	20275	151	1	0	4	5	660	440	0	3952	19610	142	10223	124	10108	125	11064	620	2856661	0	20234	20375	20416	18447	39	18835	11187	224	11162	224	33501	20404	20371	8	1	10201	100	99	100	100	10000	100	0	0	2	0	0	2	15880	0	878	0	2	73	2	5	20043	11	10000	100	20371	20374	20373	20416	20421
10204	20370	153	0	1	0	0	21	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	8	18745	10724	226	11163	230	33990	20181	20371	8	1	10201	100	99	100	100	10000	100	2	2	0	0	0	0	15985	0	867	0	3	96	2	3	20041	9	10000	100	20374	20422	20375	20372	20374
10204	20037	150	0	0	8	7	924	704	0	3448	19610	179	10219	123	10084	122	11157	615	2857765	0	20270	20419	20370	18451	39	18891	11324	232	11329	228	34008	20417	20405	8	1	10201	100	99	100	100	10000	100	2	2	2	0	0	0	13885	2	874	0	2	97	3	2	20095	9	10000	100	20317	20324	20322	20324	20326

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	1	0	0	1	0	0	0	0	1	64	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	644	8	16	6	8	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	0	1	0	0	0	0	1	64	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10162	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	6	644	9	16	9	8	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	0	1	0	0	0	0	1	64	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	9	16	6	8	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	0	1	0	0	0	0	1	64	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	642	9	16	9	9	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	0	1	0	0	0	0	1	64	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	7	16	9	9	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	0	1	0	0	0	0	1	64	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	3	642	8	16	9	9	19785	10000	10	20038	20038	20038	20038	20226
10024	20037	150	1	0	0	1	0	0	0	0	1	64	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	9	16	9	9	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	149	1	0	0	1	0	0	0	225	1	1220	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	9	16	9	9	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	0	1	0	0	0	0	1	64	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	9	16	8	8	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	0	1	0	0	0	0	2	64	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	9	16	9	10	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  tbx v0.8b, { v0.16b }, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	a9	ac	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	18	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	0	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	3	2	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20084	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	20013	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	9	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10586	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	0	710	1	16	1	1	19791	8	10000	100	20038	20038	20038	20086	20038
10204	20037	150	27	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20084	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	24	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	1	1	0	2	67	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	644	10	16	10	10	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	1	0	2	67	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	644	5	16	10	10	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	149	1	1	0	2	67	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	644	10	16	10	10	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	1	0	2	67	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	644	10	16	10	10	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	1	0	2	732	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	644	10	16	10	10	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	1	0	2	67	19687	25	10010	10	10000	10	10000	50	2847680	1	20065	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	644	10	16	10	10	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	1	0	2	67	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	644	10	16	10	10	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	1	0	2	67	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	644	10	16	10	11	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	1	0	2	67	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	644	10	16	10	5	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	1	0	2	67	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	644	10	16	10	10	19785	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->3

Code:

  tbx v0.8b, { v1.16b }, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19674	44	10129	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	30	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	12	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	37	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	420	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	27	0	61	19687	25	10100	132	10000	100	10000	500	2847680	0	20018	20132	20179	18429	3	18745	10100	208	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	6	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	103	19687	25	10100	100	10012	109	10000	500	2847680	0	20018	20084	20085	18423	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	2	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	9	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20084	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	6	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	282	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	66	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20085
10024	20083	150	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	441	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	120	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	15	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.8b, { v8.16b }, v9.8b
  movi v1.16b, 0
  tbx v1.8b, { v8.16b }, v9.8b
  movi v2.16b, 0
  tbx v2.8b, { v8.16b }, v9.8b
  movi v3.16b, 0
  tbx v3.8b, { v8.16b }, v9.8b
  movi v4.16b, 0
  tbx v4.8b, { v8.16b }, v9.8b
  movi v5.16b, 0
  tbx v5.8b, { v8.16b }, v9.8b
  movi v6.16b, 0
  tbx v6.8b, { v8.16b }, v9.8b
  movi v7.16b, 0
  tbx v7.8b, { v8.16b }, v9.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	150	0	0	0	0	0	12	0	38	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	0	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	33	0	513	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	1	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	12	0	38	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	1	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	300	0	38	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	241203	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	1	1	71	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	1	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	0	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	0	0	703	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	1	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	297	0	38	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	1	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	1	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	18	0	38	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	0	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20078	150	0	1071	616	44	27	80012	12	80000	12	80000	62	640000	0	1	0	20040	20050	20050	3	21	80012	20	80000	20	240000	20059	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10030	3	1	2	8	25	2	1	1	19	10	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	161	0	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	0	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10031	3	5	1	9	25	2	1	1	19	10	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	0	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	2	0	0	0	10042	3	1	1	19	36	1	1	1	19	21	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	15	132	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20059	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	3	1	1	7	25	2	1	1	19	10	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	139	27	80012	12	80000	12	80000	62	640000	1	1	0	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10032	13	6	1	9	34	4	2	2	9	21	20047	2	20	1	160000	10	20051	20051	20051	20051	20060
160024	20050	150	0	24	0	184	27	80012	12	80000	12	80000	62	640000	1	1	10	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10045	16	1	1	19	34	2	1	2	19	21	20047	2	20	1	160000	10	20051	20060	20060	20051	20051
160024	20050	150	0	0	0	145	27	80012	12	80000	12	80000	62	640000	0	1	10	20031	20050	20059	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	1	3	10030	13	5	1	9	25	1	2	1	7	21	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	36	0	44	27	80012	12	80000	12	80000	62	640000	1	0	10	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10042	13	5	1	19	25	2	1	1	19	21	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	39	0	44	27	80012	12	80000	12	80000	62	640000	1	0	10	20031	20059	20050	3	21	80012	20	80000	20	240000	20059	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10042	13	5	2	19	25	2	1	2	15	8	20047	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	44	27	80012	12	80000	12	80000	62	640000	1	0	10	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10042	3	6	1	19	34	2	2	1	19	10	20047	2	20	1	160000	10	20051	20051	20051	20051	20051

Test 6: throughput

Count: 16

Code:

  tbx v0.8b, { v16.16b }, v17.8b
  tbx v1.8b, { v16.16b }, v17.8b
  tbx v2.8b, { v16.16b }, v17.8b
  tbx v3.8b, { v16.16b }, v17.8b
  tbx v4.8b, { v16.16b }, v17.8b
  tbx v5.8b, { v16.16b }, v17.8b
  tbx v6.8b, { v16.16b }, v17.8b
  tbx v7.8b, { v16.16b }, v17.8b
  tbx v8.8b, { v16.16b }, v17.8b
  tbx v9.8b, { v16.16b }, v17.8b
  tbx v10.8b, { v16.16b }, v17.8b
  tbx v11.8b, { v16.16b }, v17.8b
  tbx v12.8b, { v16.16b }, v17.8b
  tbx v13.8b, { v16.16b }, v17.8b
  tbx v14.8b, { v16.16b }, v17.8b
  tbx v15.8b, { v16.16b }, v17.8b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40116	299	0	0	0	30	0	0	40	0	100	160100	100	160000	100	160000	500	5486390	0	40019	40121	40117	20026	0	3	20070	160100	200	160000	200	480000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40100	0	160000	100	40039	40104	40248	40127	40127
160204	40103	299	0	0	0	57	0	0	61	137	25	160191	100	160125	100	160485	500	5403125	1	40107	40038	40057	20012	0	3	19996	160100	200	160000	200	480000	40038	40126	1	1	160201	100	99	100	100	160000	100	0	0	0	0	3	10110	2	16	2	2	40035	0	160000	100	40098	40345	40118	40118	40118
160204	40118	300	0	0	0	306	0	125	40	0	25	160211	100	160111	100	160000	500	5403890	0	40084	40063	40038	20012	0	3	20075	160100	200	160000	200	481443	40038	40117	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	4	16	2	2	40100	0	160000	100	40039	40127	40039	40127	40104
160204	40038	301	0	0	3	30	0	0	103	0	25	160100	100	160091	100	160000	500	5486390	0	40084	40057	40066	19973	0	3	19996	160100	200	160000	200	480000	40103	40103	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40100	0	160000	100	40104	40104	40039	40104	40104
160204	40103	300	0	0	0	18	0	0	82	0	25	160100	100	160000	100	160000	500	5403125	0	40084	40038	40106	19973	0	3	20084	160100	200	160000	200	480000	40126	40103	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40100	0	160000	100	40104	40039	40127	40039	40127
160204	40038	300	0	0	0	36	0	0	705	0	25	160191	100	160088	100	160000	500	5403890	0	40019	40038	40057	19973	0	3	19996	160100	200	160000	200	480000	40038	40103	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40114	0	160000	100	40118	40118	40039	40118	40039
160204	40038	300	1	0	0	33	0	0	61	151	25	160211	100	160111	100	160000	500	1280000	1	40019	40065	40112	19976	0	3	20061	160100	200	160000	200	480000	40038	40065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40100	0	160000	100	40118	40039	40118	40118	40118
160204	40117	300	0	0	0	21	0	0	61	0	25	160211	100	160111	100	160000	500	1280000	1	40019	40038	40126	20035	0	3	20061	160100	200	160000	200	480000	40103	40038	1	1	160201	100	99	100	100	160000	100	2	0	0	0	0	10110	2	16	2	2	40035	0	160000	100	40104	40039	40104	40104	40104
160204	40126	300	0	0	0	24	0	0	61	0	25	160100	100	160091	100	160000	500	1280000	1	40084	40103	40344	19973	0	3	20075	160100	200	160000	200	480000	40117	40117	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40127	40104	40104	40104
160204	40103	300	0	0	0	27	0	0	40	149	25	160225	100	160000	100	160000	500	1280000	1	40093	40057	40126	20012	0	3	20076	160100	200	160000	200	480000	40038	40117	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40104	40039	40127	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40148	301	0	0	0	0	51	0	42	45	110	25	160092	10	160082	10	160000	50	1280000	0	1	5	40080	40038	40099	20031	3	20018	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	2	1	9	16	2	1	1	9	9	40096	0	15	5	160000	10	40100	40100	40100	40100	40100
160024	40039	300	0	0	0	0	0	0	82	73	0	25	160092	10	160082	10	160000	50	5402633	0	1	5	40080	40038	40099	20079	3	20079	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	2	1	8	16	2	1	1	8	6	40096	0	15	5	160000	10	40100	40100	40100	40039	40100
160024	40038	299	0	0	0	0	0	0	109	45	0	25	160092	10	160082	10	160000	50	5402633	1	1	5	40080	40038	40099	19996	3	20079	160010	20	160000	20	480000	40038	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10024	11	3	2	6	16	4	2	2	6	9	40096	0	30	10	160000	10	40100	40100	40100	40100	40100
160024	40099	300	0	0	0	0	0	0	82	67	110	25	160092	10	160082	10	160000	50	5402633	1	1	5	40080	40038	40099	19996	3	20079	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	2	1	4	16	2	1	1	9	8	40096	0	15	5	160000	10	40100	40100	40100	40100	40100
160024	40099	301	0	0	0	0	0	0	82	710	110	25	160092	10	160082	10	160000	50	5402633	1	1	5	40080	40038	40038	19996	3	20121	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	1	0	10022	8	2	1	6	16	2	1	1	9	8	40096	0	15	5	160000	10	40100	40100	40100	40100	40100
160024	40099	300	0	0	0	0	0	0	82	67	0	25	160092	10	160082	10	160000	50	1280000	1	1	5	40080	40038	40099	20031	3	20079	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	2	1	6	16	2	1	1	8	5	40096	0	15	6	160000	10	40100	40100	40100	40100	40100
160024	40099	300	0	0	0	0	0	0	0	45	0	25	160092	10	160000	10	160000	50	5402633	1	1	5	40080	40038	40074	20031	3	20018	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10024	11	3	2	5	16	4	2	2	8	8	40096	0	30	10	160000	10	40100	40100	40100	40100	40100
160024	40099	300	0	0	0	0	18	0	0	51	0	25	160092	10	160082	10	160000	50	5402633	0	1	5	40080	40038	40038	20031	3	20079	160010	20	160000	20	480000	40038	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10024	10	3	2	9	16	4	2	2	6	4	40096	0	30	10	160000	10	40149	40040	40102	40039	40100
160024	40099	300	0	0	0	0	60	0	82	51	110	25	160010	10	160000	10	160000	50	1280000	0	1	5	40080	40039	40141	20031	11	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10024	11	3	2	4	16	4	2	2	4	6	40145	1	30	11	160000	10	40151	40249	40112	40219	40100
160024	40099	300	0	0	0	0	0	0	82	51	0	25	160010	10	160000	10	160000	50	5402633	0	1	5	40080	40038	40071	19996	3	20336	160010	20	160000	20	480000	40099	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10024	11	3	2	6	16	4	2	2	8	5	40096	0	30	10	160000	10	40100	40100	40100	40100	40039

TBX (single register table, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations