Firestorm: TBX (three register table, 16B) measurements

Code:

  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 3.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
3004	6037	45	0	82	5687	25	3000	3000	3000	838680	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	46	0	61	5687	25	3000	3000	3000	838680	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6073	45	0	84	5687	25	3000	3000	3000	838680	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	5	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	16	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	73	2	16	4	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	3	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	2	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038

Test 2: Latency 1->1

Code:

  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	60037	450	12	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55937	7	56240	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	16	59795	0	30000	100	60038	60038	60038	60038	60038
30204	60037	449	12	205	59687	25	30100	100	30000	100	30000	500	8587680	0	60018	60037	60037	55929	7	56241	30100	200	30680	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	2	0	0	1	1	1	774	16	59796	14	30000	100	60038	60038	60038	60038	60038
30204	60037	450	0	103	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56241	30100	200	30674	200	90024	60037	60037	2	1	10201	100	99	100	100	10000	100	0	0	2	1	1	1	717	16	59795	0	30000	100	60038	60038	60038	60038	60038
30204	60037	450	0	61	59687	25	30100	100	30000	100	30456	500	8587680	0	60018	60037	60037	55929	7	56240	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	2	3	0	1	1	1	716	16	59795	0	30000	100	60038	60038	60038	60038	60038
30204	60037	449	195	388	59687	25	30100	100	30000	100	30000	505	8587680	1	60018	60037	60037	55929	7	56240	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	2	9	0	1	1	1	716	16	59796	0	30000	100	60038	60038	60038	60038	60038
30204	60037	450	0	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56240	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	716	16	59795	0	30000	100	60038	60038	60038	60038	60038
30204	60037	449	0	536	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56241	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	16	59795	0	30000	100	60038	60038	60038	60038	60038
30204	60037	449	0	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56240	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	16	59795	0	30000	100	60038	60038	60038	60038	60038
30204	60037	450	486	768	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56240	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	3	0	1	1	1	716	16	59796	0	30000	100	60038	60038	60038	60038	60038
30204	60037	465	0	61	59687	25	30100	100	30000	100	30000	532	8587680	1	60018	60037	60037	55929	7	56241	30100	200	30008	200	90024	60183	60037	1	1	10201	100	99	100	100	10000	100	1	9	0	1	1	1	716	16	59795	0	30000	100	60038	60038	60038	60038	60038

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	60037	450	0	0	0	0	0	0	0	0	61	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	4	16	4	4	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	449	0	0	0	0	0	0	0	0	61	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	4	16	4	4	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	450	0	0	0	0	0	0	0	0	61	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	60037	60037	55944	10	56304	30618	20	30333	20	91488	60085	60086	1	1	10021	10	9	10	10	10000	10	0	0	0	1	6	0	640	4	16	4	4	59785	0	30000	10	60038	60038	60038	60185	60038
30024	60037	449	0	0	0	0	0	0	0	0	210	59687	25	30010	10	30000	10	30000	50	8588963	1	60018	60037	60037	55944	12	56285	30466	20	30162	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	4	16	4	4	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	450	0	0	0	0	0	0	0	0	61	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	4	16	4	4	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	450	0	0	0	0	0	0	0	0	747	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	4	16	4	4	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	450	0	0	0	0	0	0	0	0	61	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	4	16	4	5	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	450	0	0	0	0	0	0	12	0	61	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	3	0	640	10	35	7	5	59825	0	30000	10	60134	60087	60038	60038	60184
30024	60037	450	0	1	0	1	0	0	0	0	166	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	640	5	16	5	4	59849	0	30000	10	60038	60038	60038	60038	60038
30024	60037	450	0	0	0	0	0	0	0	0	768	59687	25	30010	10	30000	10	30000	50	8587680	0	60018	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	640	4	16	5	4	59785	0	30000	10	60038	60038	60038	60038	60038

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	79	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	da	dd	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50204	80038	599	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	5	80019	80038	80038	73428	6	73740	40125	0	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1	1	1	1916	5	1	0	17	0	0	79809	25	50000	100	80039	80039	80039	80247	80039
50204	80038	599	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	5	80019	80038	80038	73428	7	73740	40125	0	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1	1	1	1916	5	1	0	16	0	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	5	80019	80038	80038	73423	7	73740	40125	0	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1	1	1	1916	5	1	0	16	0	1	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	5	80019	80038	80038	73428	6	73740	40125	0	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	2	26318	0	1	1	1	2267	5	1	1	170	0	0	80509	24	50000	100	80733	81006	81009	81054	81002
50204	81048	607	1	20	20	2517	1760	147	79472	465	40363	133	40228	125	43040	644	11481772	1	5	80780	80993	81058	73398	110	74063	43171	0	228	42485	220	118677	81111	80796	21	1	30201	100	99	100	100	30000	100	0	2	1	1	0	50718	0	1	1	1	2265	5	1	0	173	0	0	80729	21	50000	100	81313	81310	81000	81317	81212
50204	81263	609	1	31	23	0	0	11751	79447	446	40421	133	40228	126	44712	626	11485725	1	5	80671	80997	81513	73392	226	74167	43773	0	226	42977	226	120025	81403	81209	28	1	30201	100	99	100	100	30000	100	2	2	0	1	2	54558	0	1	1	1	1937	5	1	0	145	0	0	80584	25	50000	100	80039	80039	80039	80039	80039
50204	80089	621	0	0	0	0	0	194	79686	26	40139	125	40000	125	40000	625	11457640	1	5	80019	80038	80038	73427	6	73741	40125	8	200	40174	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1	1	1	1916	5	1	0	16	0	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	5	80019	80038	80038	73428	6	73740	40125	0	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1	1	1	1917	5	1	0	16	0	0	79809	25	50000	100	80039	80039	80039	80039	80091
50204	80038	599	0	0	0	0	0	251	79686	26	40125	125	40000	125	40000	625	11457640	1	5	80019	80038	80038	73428	7	73740	40125	0	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1	1	1	1916	5	1	0	16	0	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	0	0	726	79686	26	40125	125	40000	125	40000	625	11457640	1	5	80019	80038	80038	73428	6	73741	40125	0	200	40174	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1	1	1	1916	5	1	0	16	0	0	79809	25	50000	100	80039	80039	80039	80039	80039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50024	80038	600	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	5	17	4	4	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	0	654	0	61	79686	26	40013	13	40000	13	40000	65	11457640	1	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	9	17	3	4	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80291	600	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	1	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	4	17	3	5	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	4	17	3	4	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	4	17	3	4	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	4	17	3	5	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	5	17	4	4	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	0	0	0	726	79686	26	40025	13	40000	13	40000	65	11457640	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	4	17	3	4	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	0	0	0	726	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	4	17	4	4	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11458037	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	5	17	3	4	79796	3	50000	10	80039	80039	80039	80039	80039

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50204	60043	449	0	0	0	9	61	59696	26	40125	125	40000	125	40000	625	8577118	60021	0	60040	60040	53439	7	53742	40125	200	40007	200	110020	60040	60043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1	1	1	1916	0	16	0	59895	25	50000	100	60041	60044	60044	60041	60041
50204	60040	450	0	0	0	0	61	59696	26	40125	125	40000	125	40000	625	8576687	60021	0	60095	60040	53439	6	53743	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1	1	1	1917	0	16	0	59838	25	50000	100	60041	60041	60041	60041	60044
50204	60040	449	0	12	0	9	61	59696	26	40125	125	40000	125	40000	625	8576687	60021	0	60040	60040	53439	7	53743	40125	200	40007	200	110020	60040	60043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1	1	1	1917	0	16	0	59834	25	50000	100	60041	60041	60041	60041	60041
50204	60040	450	0	0	0	0	61	59717	26	40134	125	40009	125	40000	625	8576725	60021	0	60040	60040	53439	6	53743	40125	200	40007	200	110020	60040	60043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1	1	1	1917	0	16	0	59834	25	50000	100	60041	60041	60041	60041	60044
50204	60040	450	0	0	0	0	61	59696	26	40125	125	40001	125	40000	625	8576687	60021	0	60043	60040	53439	7	53743	40125	200	40007	200	110020	60040	60043	1	1	30201	100	99	100	100	30000	100	2	2	0	0	0	0	1	1	1	1917	0	16	0	59834	25	50000	100	60041	60041	60044	60041	60041
50204	60040	450	0	0	0	9	61	59696	26	40125	125	40000	125	40000	625	8576725	60021	0	60040	60040	53439	7	53742	40125	200	40007	200	110020	60040	60040	1	1	30202	100	99	100	100	30000	100	0	0	0	2	0	0	1	1	1	1917	0	16	0	59835	25	50000	100	60041	60041	60041	60041	60041
50204	60040	449	0	0	0	0	61	59696	26	40126	125	40000	125	40000	625	8576687	60021	0	60040	60043	53439	6	53746	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1	1	1	1916	0	16	0	59838	25	50000	100	60041	60041	60041	60041	60041
50204	60040	450	0	0	0	0	61	59696	26	40125	125	40000	125	40000	625	8576687	60021	0	60040	60040	53439	7	53742	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1	1	1	1917	0	16	0	59834	25	50000	100	60041	60041	60044	60041	60041
50204	60040	449	0	0	0	1	61	59696	26	40125	125	40000	125	40000	625	8576687	60021	0	60040	60040	53442	6	53742	40125	200	40007	200	110020	60043	60040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	1	1	1	1917	0	16	0	59835	25	50000	100	60044	60041	60044	60044	60044
50204	60040	449	0	0	0	0	61	59696	26	40125	125	40000	125	40000	625	8576687	60021	0	60040	60040	53439	6	53743	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	2	0	0	0	0	0	1	1	1	1917	0	24	0	59834	25	50000	100	60044	60041	60041	60041	60041

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50024	60040	450	0	0	0	0	0	0	1	61	59696	26	40013	13	40001	13	40000	65	8576687	1	60021	0	60040	60043	53454	3	53769	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	7	17	5	6	59826	3	50000	10	60041	60041	60041	60044	60041
50024	60040	450	0	0	0	0	9	0	0	61	59696	26	40013	13	40000	13	40000	65	8576687	1	60021	0	60040	60040	53454	3	53769	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	2	0	0	0	0	0	1890	6	17	4	6	59826	3	50000	10	60041	60041	60044	60041	60041
50024	60043	449	0	0	0	0	0	0	0	61	59696	26	40013	13	40000	13	40000	65	8576687	1	60024	0	60040	60040	53457	3	53772	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	6	17	4	5	59826	3	50000	10	60044	60041	60041	60041	60041
50024	60040	450	0	0	0	0	0	0	0	61	59696	26	40013	13	40000	13	40000	65	8576687	1	60024	0	60043	60043	53457	3	53772	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	5	17	4	5	59826	3	50000	10	60041	60041	60041	60041	60041
50024	60040	450	0	0	0	0	0	0	0	61	59696	26	40013	13	40001	13	40000	65	8576687	1	60021	0	60040	60040	53457	3	53769	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	5	17	5	5	59826	3	50000	10	60041	60041	60044	60041	60041
50024	60040	450	0	0	0	0	0	0	0	61	59696	26	40013	13	40001	13	40000	65	8576687	1	60021	0	60040	60040	53454	3	53769	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	5	17	4	5	59826	3	50000	10	60041	60044	60041	60041	60041
50024	60040	449	0	0	0	0	51	0	1	255	59696	26	40013	13	40001	13	40000	65	8576687	1	60021	0	60043	60043	53454	3	53769	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1	0	1890	6	17	5	6	59826	3	50000	10	60041	60044	60041	60041	60041
50024	60040	449	0	0	0	0	0	0	0	61	59696	26	40013	13	40000	13	40000	65	8576687	1	60021	0	60040	60040	53454	3	53769	40013	20	40000	20	110000	60040	60043	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	3	0	0	0	1890	5	17	4	5	59826	3	50000	10	60041	60041	60044	60041	60041
50024	60040	450	0	0	0	0	0	0	0	726	59696	26	40014	13	40009	13	40000	65	8576687	1	60021	0	60040	60043	53454	3	53769	40013	20	40000	20	110000	60043	60043	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	6	17	5	6	59826	3	50000	10	60041	60041	60044	60041	60041
50024	60040	449	0	0	0	0	0	0	0	61	59696	26	40013	13	40000	13	40000	65	8576687	1	60021	0	60040	60040	53457	3	53772	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	6	17	5	5	59826	3	50000	10	60041	60041	60041	60041	60041

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0042

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50204	40042	300	0	3	388	39685	26	40127	125	40003	125	40000	625	5692152	1	40023	40042	40042	33453	7	33743	40125	200	40007	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	3	61	39687	26	40128	125	40001	125	40000	625	5692281	0	40023	40109	40042	33453	7	33743	40125	200	40007	200	110036	40042	40042	1	1	30201	100	99	100	100	30000	100	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	24	0	61	39684	26	40125	125	40001	125	40000	625	5692272	1	40023	40042	40042	33453	6	33744	40125	200	40007	200	110036	40042	40100	1	1	30201	100	99	100	100	30000	100	0	1	1	1	1916	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	299	0	1	61	39685	26	40127	125	40000	125	40000	625	5693538	1	40023	40042	40042	33453	7	33744	40125	200	40007	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	1	1	1	1916	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	2	61	39687	26	40128	125	40002	125	40000	625	5692208	1	40023	40042	40042	33453	7	33744	40125	200	40007	200	110036	40042	40042	1	1	30201	100	99	100	100	30000	100	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	4	271	39685	26	40126	125	40003	125	40000	625	5693510	1	40023	40042	40042	33453	7	33743	40125	200	40007	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	2	103	39685	26	40128	125	40003	125	40000	625	5692195	1	40023	40042	40042	33453	7	33743	40125	200	40013	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	1	1	1	1916	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	9	1	84	39685	26	40129	125	40001	125	40000	625	5693444	1	40023	40042	40042	33453	7	33743	40125	200	40007	200	110036	40042	40042	1	1	30201	100	99	100	100	30000	100	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	3	208	39687	26	40129	125	40001	125	40000	625	5692066	1	40023	40042	40042	33453	7	33744	40125	200	40007	200	110036	40042	40042	1	1	30201	100	99	100	100	30000	100	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	3	523	39685	26	40126	125	40004	125	40000	625	5692294	1	40023	40042	40042	33453	7	33743	40125	200	40007	200	110036	40042	40042	1	1	30201	100	99	100	100	30000	100	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0042

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50024	40042	299	1	0	21	0	1408	39685	26	40016	13	40002	13	40000	65	5692152	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	2	1	0	3	0	1892	8	17	7	9	39871	3	0	50000	10	40043	40043	40043	40043	40043
50024	40042	300	1	0	6	3	105	39684	26	40016	13	40001	13	40000	65	5692296	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	1	0	6	0	1892	11	17	12	12	39871	3	0	50000	10	40043	40043	40043	40043	40043
50024	40042	300	1	0	15	3	107	39687	26	40013	13	40004	13	40000	65	5693436	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	1	0	6	0	1892	11	17	7	13	39871	3	0	50000	10	40043	40043	40043	40043	40043
50024	40042	300	1	0	15	0	157	39685	26	40015	13	40002	13	40000	65	5692290	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	3	0	1890	9	17	11	11	39871	3	0	50000	10	40043	40043	40043	40043	40043
50024	40042	300	1	0	21	2	161	39685	26	40015	13	40002	13	40000	65	5693436	1	40023	40042	40042	33469	3	33807	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	2	0	0	0	1892	10	17	8	11	39871	3	0	50000	10	40043	40043	40043	40043	40043
50024	40042	300	1	0	15	1	107	39685	26	40014	13	40002	13	40000	65	5693510	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	1	0	3	0	1892	10	17	8	11	39871	3	0	50000	10	40043	40043	40043	40043	40043
50024	40042	300	1	0	6	2	743	39685	26	40015	13	40002	13	40000	65	5692193	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	1	0	0	0	1892	11	17	12	9	39871	3	0	50000	10	40043	40043	40043	40043	40043
50024	40042	299	1	0	21	2	105	39687	26	40014	13	40002	13	40000	65	5692728	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	2	0	3	0	1892	8	17	11	7	39871	3	0	50000	10	40043	40306	40043	40043	40043
50024	40042	300	1	0	117	4	621	39687	26	40016	13	40003	13	40000	65	5693429	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	14	0	0	0	1892	11	17	11	8	39871	3	0	50000	10	40043	40043	40043	40043	40043
50024	40042	300	1	0	15	3	84	39684	26	40015	13	40002	13	40000	65	5693436	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	6	0	1892	11	17	11	11	39871	3	0	50000	10	40043	40043	40043	40043	40043

Test 6: Latency 1->5

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b
  add v4.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50204	80038	599	0	0	0	187	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	80038	80038	73428	0	7	73740	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	80038	80038	73428	0	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	9	0	82	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	80038	80038	73428	0	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	253	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	80038	80038	73428	0	7	73740	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	80038	80038	73428	0	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	2	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	80019	80038	80038	73428	0	7	73740	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	80019	80038	80038	73428	0	7	73740	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	16	0	79809	25	50000	100	80039	80039	80093	80039	80091
50204	80038	599	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	80038	80038	73428	0	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	80038	80038	73428	0	7	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	389	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	80038	80038	73428	0	7	73740	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80039	80039	80039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50024	80038	599	0	0	462	79485	365	40239	14	40228	11	42888	87	11480555	0	1	80565	80896	80902	73404	138	74077	42907	20	43117	20	118645	81056	81051	20	1	30021	10	9	10	10	30000	10	4	2	2	1	0	0	38708	4	1890	0	0	3	17	0	3	4	79872	3	0	0	50000	10	80039	80039	80039	80039	80649
50024	80038	643	0	0	5241	79553	226	40119	14	40168	14	44408	66	11496751	0	0	80855	81447	81669	73371	3	73929	43203	24	44787	22	121284	81414	81202	27	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	3	0	1890	0	0	3	17	0	3	3	79796	3	0	0	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	61	79686	26	40013	13	40036	13	40000	65	11457640	0	1	80019	80038	80038	73443	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	0	3	17	0	3	3	79796	3	0	0	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	1	1	80019	80038	80038	73443	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	0	3	17	0	3	3	79796	3	0	0	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	45	82	79686	26	40013	13	40000	13	40000	65	11457640	0	1	80019	80038	80038	73443	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	0	3	17	0	4	3	79796	3	0	0	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	1	80019	80038	80038	73443	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	0	3	17	0	3	3	79796	3	0	0	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	190	79686	26	40013	13	40000	13	40000	65	11457640	0	1	80019	80038	80038	73443	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	0	4	17	0	3	4	79796	3	0	0	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	726	79686	26	40013	13	40000	13	40000	65	11457640	0	1	80019	80038	80038	73443	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	0	3	17	0	3	3	79796	3	0	0	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	726	79686	26	40013	13	40000	13	40000	65	11457640	0	1	80019	80038	80038	73443	32	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	0	3	17	0	3	3	79796	3	0	0	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	33	193	79686	26	40013	13	40000	13	40000	65	11457640	0	0	80019	80038	80038	73443	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	0	3	17	0	3	3	79796	3	0	0	50000	10	80039	80039	80039	80039	80039

Test 7: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v1.16b, 0
  tbx v1.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v2.16b, 0
  tbx v2.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v3.16b, 0
  tbx v3.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v4.16b, 0
  tbx v4.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v5.16b, 0
  tbx v5.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v6.16b, 0
  tbx v6.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v7.16b, 0
  tbx v7.16b, { v8.16b, v9.16b, v10.16b }, v11.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320204	81484	613	0	0	0	0	238	0	26	240125	125	240000	125	240000	636	3299571	60028	0	60047	60047	19973	0	3	20004	240257	200	240000	200	720000	60047	81588	1	1	160201	100	99	100	100	160000	100	2	2	0	0	0	9	0	0	10110	2	16	1	1	60044	25	320000	100	60048	60048	60048	60048	60048
320204	60047	449	4	552	0	0	132	0	26	240125	125	240000	125	240000	625	3299571	60028	3	81643	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	12	0	0	10110	1	16	1	1	60044	25	320000	100	81239	60048	60048	60048	60048
320204	60047	450	0	0	0	0	48	0	26	240125	125	240000	125	240000	625	3299571	60028	0	60047	60047	41099	0	3	41195	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	6	0	0	10110	1	16	1	1	60044	25	320000	100	60048	60048	60048	60048	81190
320204	60047	450	0	12	0	0	61	0	26	240125	125	289154	125	240000	625	3299571	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	0	0	10110	2	16	2	1	60044	25	320000	100	60048	60048	60048	81239	60048
320204	60047	450	0	0	0	0	713	0	26	240125	125	240000	125	240000	625	3299571	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	81238	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	1	1	60044	25	320000	100	60048	60048	81239	60048	81190
320204	60047	450	0	3	0	0	734	0	26	240125	125	240000	125	240000	625	3299571	60028	0	60047	60047	20011	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	2	16	1	1	60044	25	320000	100	60048	60048	60048	60284	60048
320204	60047	450	0	0	0	0	726	0	26	240125	125	240000	125	240000	625	3299571	60028	0	60108	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	17	1	1	60044	25	320000	100	60048	60048	60048	60048	81239
320204	60047	450	0	0	0	0	48	0	26	240125	125	240000	125	240000	625	3299571	60028	0	81825	60047	19973	0	3	20004	240125	200	240000	200	720402	60164	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	1	1	60044	25	320000	100	60048	60048	60048	60048	60048
320204	60047	450	0	147	88	0	48	0	26	240125	125	289154	125	240000	625	11428114	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	0	0	0	10110	2	16	1	1	60044	25	320000	100	60048	60048	60048	81484	60048
320204	60047	449	0	0	0	0	48	58354	26	240125	125	240000	125	240000	625	3299571	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	1	1	60044	25	320000	100	60048	60048	60048	60048	60048

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	09	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320024	60048	450	1	0	0	0	0	0	0	0	53	0	26	240013	13	240000	13	240000	65	3299571	1	1	0	60028	0	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	1	0	3	0	10023	3	1	1	1	39	17	1	1	1	25	27	60044	3	16	140	320000	10	81450	81700	81294	60048	60048
320024	60047	450	1	1	0	0	0	12	0	0	53	0	54	240229	13	240000	13	240000	67	3299571	1	1	5	60028	0	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	8	4	1	1	25	17	1	1	1	20	25	60044	3	16	138	320000	10	81706	81338	60048	60048	60048
320024	60047	450	1	1	1	0	0	0	0	0	268	0	26	240013	13	240000	13	240000	65	3299571	1	1	5	60028	0	60047	60047	20004	0	14	20109	241053	20	240000	20	720000	60047	60351	4	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	8	4	1	1	25	17	1	1	1	22	25	60044	3	16	135	320000	10	60048	60048	60048	60347	81504
320024	60047	449	0	0	0	0	0	0	0	0	53	58295	26	240013	13	240000	14	240000	65	3302093	1	1	5	60028	0	60047	81096	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	8	5	1	1	26	17	1	1	1	16	25	60044	3	16	127	320000	10	60048	60048	60048	60048	60048
320024	60047	450	1	1	0	0	0	0	0	0	112	0	26	240013	13	240000	13	240000	65	3299571	1	1	5	60028	3	60047	60047	19996	9	3	20026	240013	20	240000	20	720000	60047	60047	2	1	160021	10	9	10	10	160000	10	0	0	0	201	1	10022	8	4	1	0	34	17	1	1	1	26	26	60044	3	16	7	320000	10	60048	60048	60048	60048	60048
320024	60047	449	0	0	0	0	0	0	0	0	224	0	26	240013	13	240000	13	240000	65	3299571	1	0	0	60028	0	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	1	10023	3	1	1	1	26	17	1	1	2	28	18	60044	3	16	7	320000	10	60048	60048	60048	60048	60048
320024	60047	450	1	1	0	0	0	0	0	0	98	0	26	240013	13	240000	13	240000	65	3299571	1	0	0	60028	0	81161	60047	19996	0	35	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	3	1	1	1	25	17	1	1	1	21	26	60044	3	16	7	320000	10	60048	60048	60048	60048	60048
320024	60047	450	1	1	0	0	0	0	0	0	203	0	26	240013	13	240000	13	240000	65	3299571	1	0	0	60028	0	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	3	1	1	1	26	17	1	1	1	25	26	60044	3	16	7	320000	10	60048	60048	60048	60048	60048
320024	60047	450	1	1	0	0	0	0	0	0	795	0	26	290148	13	240000	13	240000	65	3299571	0	0	0	60028	0	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	3	1	2	1	16	17	1	1	1	21	25	60044	3	16	14	320000	10	60048	60048	60048	60048	60048
320024	60047	449	1	1	0	0	0	21	0	0	98	0	26	240013	13	240000	13	240000	65	3299571	1	0	0	60028	0	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	6	2	0	0	10023	3	1	1	1	26	17	1	1	1	17	27	60044	3	16	13	320000	10	60048	60048	60048	60048	60048

TBX (three register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations