Firestorm: TBX (three register table, 8B) measurements

Code:

  tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 3.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	0	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	1	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	0	6018	6037	6037	5322	3	5645	3000	3000	9486	6037	6037	1	1	1001	1000	0	0	0	0	73	2	16	2	2	5824	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	0	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	0	0	73	2	16	2	2	5853	3000	6038	6038	6038	6038	6038
3004	6037	46	0	61	5687	25	3000	3000	3000	838680	0	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3012	3000	3000	838680	1	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	0	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	0	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	61	5687	25	3000	3000	3000	838680	0	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038
3004	6037	45	0	84	5687	25	3000	3000	3000	838680	0	6018	6037	6037	5322	3	5645	3000	3000	9000	6037	6037	1	1	1001	1000	0	0	0	0	73	2	16	2	2	5787	3000	6038	6038	6038	6038	6038

Test 2: Latency 1->1

Code:

  tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	60037	450	0	0	0	0	0	0	0	726	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56240	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	59796	0	0	30000	100	60038	60038	60038	60038	60038
30204	60037	450	0	0	0	0	0	0	0	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56241	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	1	59795	0	0	30000	100	60038	60038	60038	60038	60038
30204	60037	449	0	0	0	0	0	0	0	89	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	7	56241	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	716	0	16	1	59795	0	0	30000	100	60038	60038	60038	60038	60038
30204	60037	450	0	0	0	0	42	0	0	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56241	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	59795	0	0	30000	100	60038	60038	60038	60038	60038
30204	60037	450	0	0	0	0	0	0	0	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56241	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	716	0	16	0	59796	0	0	30000	100	60038	60038	60038	60038	60083
30204	60037	450	0	0	0	0	0	0	0	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	7	56240	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	716	0	16	0	59796	0	0	30000	100	60038	60038	60038	60038	60038
30204	60037	449	0	0	0	0	0	0	0	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	7	56241	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	1	59795	0	0	30000	100	60038	60038	60038	60038	60038
30204	60037	450	0	0	0	0	0	0	0	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56241	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	1	59795	0	0	30000	100	60038	60038	60038	60038	60038
30204	60037	450	0	0	0	0	0	0	0	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55929	6	56241	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	716	0	16	0	59796	0	0	30000	100	60038	60038	60038	60038	60038
30204	60037	450	0	0	0	0	0	0	0	61	59687	25	30100	100	30000	100	30000	500	8587680	1	60018	60037	60037	55932	7	56240	30100	200	30008	200	90024	60037	60037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	1	59795	0	0	30000	100	60038	60038	60038	60038	60038

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	60037	450	0	0	0	0	0	0	0	321	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	0	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	449	0	0	0	0	0	0	0	193	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	0	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	0	0	640	2	16	2	2	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	449	0	0	0	0	0	0	0	145	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	0	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	3	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	449	0	0	0	0	0	0	0	124	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	0	60037	60037	55944	3	56267	30163	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	2	2	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	450	0	0	0	0	0	0	0	61	59687	25	30010	10	30000	10	30000	50	8587680	1	60018	0	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	450	0	0	0	0	0	0	0	409	59533	296	30146	15	30156	17	32128	77	8605642	1	60558	0	60700	60713	55985	64	56528	32145	24	32311	20	96951	60716	60716	15	1	10021	10	9	10	10	10000	10	0	0	2	0	4	30268	2	841	2	80	3	2	60341	5	30000	10	60038	60038	60086	60038	60038
30024	60037	450	0	0	1	0	1848	1232	0	6752	59533	255	30180	12	30180	14	31672	55	8606925	1	60558	0	60750	60719	55990	62	56495	32291	20	32479	24	97404	60475	60903	16	1	10021	10	9	10	10	10000	10	0	4	0	1	0	33960	0	881	4	179	5	3	60433	1	30000	10	61204	61147	60812	61100	61147
30024	61185	474	1	0	0	0	0	0	1	5318	59566	319	30142	14	30192	10	30000	50	8587680	1	60738	3	60797	60811	56010	71	56565	32445	20	32473	22	96447	60713	60811	13	1	10021	10	9	10	10	10000	10	0	0	0	0	0	1998	4	640	1	137	2	2	59785	1	30000	10	60038	60038	60038	60038	60038
30024	60037	465	0	0	0	1	12	0	0	1411	59676	25	30010	10	30000	10	30000	50	8587680	1	60018	0	60037	60085	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	59785	0	30000	10	60038	60038	60038	60038	60038
30024	60037	450	0	0	0	0	0	0	0	145	59687	25	30010	12	30000	10	30000	50	8591529	1	60018	0	60037	60037	55944	3	56267	30010	20	30000	20	90000	60037	60037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	59785	0	30000	10	60038	60038	60038	60038	60038

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v4.8b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50204	80038	600	0	0	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	0	80038	80092	73428	7	73740	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	0	0	0	0	129	79686	26	40125	125	40000	125	40000	625	11457640	1	80019	0	80038	80038	73428	7	73740	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	0	80038	80038	73424	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	80019	3	80038	80038	73431	7	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	0	0	0	0	726	79686	26	40125	125	40000	125	40000	625	11457640	1	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	0	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	16	0	79809	25	50000	100	80039	80039	80243	80039	80039
50204	80038	599	0	0	0	4	12	0	0	105	79686	119	40125	125	40000	125	40608	625	11457640	1	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	0	0	0	0	103	79686	26	40125	125	40000	125	40000	625	11457640	0	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	16	0	79809	25	50000	100	80039	80039	80092	80039	80039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50024	80038	599	0	0	0	0	726	79686	26	40013	13	40000	13	40000	65	11457640	0	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1890	5	17	3	5	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	9	0	726	79686	26	40013	13	40000	13	40000	65	11457842	0	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1890	5	17	5	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	61	79665	26	40013	13	40000	13	40000	65	11457640	0	1	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	3	0	0	0	1890	3	17	3	5	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1890	5	17	5	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	0	0	61	79686	26	40013	13	40000	13	40000	60	11457640	0	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1890	5	17	3	5	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1890	5	17	5	8	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	0	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1890	5	17	5	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	0	80019	0	80038	80038	73443	7	3	73767	40013	20	40000	20	110000	80092	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1890	5	17	5	7	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80091	599	0	0	0	0	726	79686	26	40013	13	40000	13	40000	65	11457640	1	1	80019	0	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1890	3	17	5	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	0	0	536	79686	26	40013	13	40000	13	40000	65	11457640	0	0	80019	0	80038	80038	73443	7	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	1890	3	17	5	3	79796	3	50000	10	80039	80039	80039	80039	80039

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v4.8b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50204	60040	450	0	0	0	0	0	0	0	61	59696	26	40125	125	40000	125	40000	625	8576687	0	60021	60040	60040	53439	7	53745	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	0	246	0	1	1	1	1916	16	59834	25	50000	100	60041	60041	60041	60041	60041
50204	60040	450	0	0	0	0	0	0	0	61	59696	26	40125	125	40000	125	40000	593	8576687	0	60021	60040	60040	53442	7	53742	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	0	252	0	1	1	1	1916	16	59835	25	50000	100	60041	60041	60041	60041	60041
50204	60040	450	0	0	0	0	0	0	0	61	59696	26	40125	125	40000	125	40000	625	8576687	0	60021	60040	60040	53439	7	53742	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	0	246	0	1	1	1	1917	16	59835	25	50000	100	60041	60041	60041	60041	60041
50204	60040	450	0	0	0	0	0	0	0	61	59696	26	40126	125	40000	125	40000	625	8576687	0	60021	60040	60040	53439	7	53742	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	0	102	0	1	1	1	1916	16	59834	25	50000	100	60041	60044	60041	60041	60041
50204	60040	450	0	0	0	0	132	0	0	61	59696	26	40125	125	40000	125	40000	625	8576687	1	60021	60043	60040	53439	6	53743	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	0	60	0	1	1	1	1917	16	59838	25	50000	100	60041	60041	60044	60041	60041
50204	60040	450	0	0	0	0	0	0	0	61	59696	26	40125	125	40000	125	40000	625	8576687	0	60021	60040	60043	53439	6	53742	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	0	234	0	1	1	1	1917	16	59838	25	50000	100	60041	60153	60153	60044	60041
50204	60150	451	0	1	0	0	276	0	0	797	59686	26	40126	125	40000	125	40000	625	8576687	0	60021	60040	60040	53442	7	53743	40125	200	40007	200	110020	60043	60040	1	1	30201	100	99	100	100	30000	100	0	0	3	0	1	1	1	1916	16	59835	25	50000	100	60041	60044	60041	60041	60041
50204	60040	450	0	0	0	0	0	0	0	726	59696	26	40125	125	40000	125	40000	625	8577118	0	60021	60040	60040	53439	6	53742	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	1	3	0	1	1	1	1917	16	59834	25	50000	100	60041	60041	60041	60041	60041
50204	60043	450	0	0	0	0	0	0	1	61	59717	26	40125	125	40000	125	40000	625	8576687	1	60021	60040	60040	53442	7	53742	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	0	231	0	1	1	1	1916	16	59837	25	50000	100	60041	60041	60041	60041	60041
50204	60043	450	0	0	0	0	0	0	0	61	59696	26	40125	125	40000	125	40000	625	8576687	0	60021	60040	60040	53442	7	53742	40125	200	40007	200	110020	60040	60040	1	1	30201	100	99	100	100	30000	100	0	2	171	0	1	1	1	1916	16	59834	25	50000	100	60041	60041	60041	60041	60041

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50024	60043	450	0	0	0	0	0	0	61	59696	26	40013	13	40000	13	41005	65	8576687	1	60021	60040	60267	53454	23	53769	40013	20	40000	20	112341	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	9	0	1890	4	33	2	2	59826	2	50000	10	60041	60041	60041	60041	60041
50024	60040	450	0	0	0	0	0	5	61	59696	26	40013	13	40000	13	40000	65	8576687	1	60021	60040	60040	53454	3	53828	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1890	2	17	3	2	59826	3	50000	10	60041	60041	60041	60041	60041
50024	60040	449	0	0	0	0	0	0	61	59696	26	40013	13	40000	13	40000	65	8576687	0	60021	60040	60040	53454	3	53769	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1890	2	17	2	2	59826	3	50000	10	60041	60044	60041	60041	60041
50024	60040	449	0	0	4	0	0	0	61	59696	26	40013	13	40001	13	40804	65	8576687	1	60021	60040	60040	53454	3	53769	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	1	3	0	1890	2	17	3	2	59826	3	50000	10	60044	60041	60041	60041	60044
50024	60040	450	0	0	0	0	0	1	61	59696	26	40013	13	40001	13	40000	65	8576687	0	60021	60040	60040	53454	3	53769	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1890	2	17	2	2	59826	3	50000	10	60041	60041	60041	60041	60041
50024	60040	449	0	0	0	0	0	0	61	59696	26	40013	13	40000	13	40000	81	8576687	1	60021	60040	60040	53454	3	53769	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1911	2	17	2	2	59826	3	50000	10	60041	60041	60041	60041	60041
50024	60212	449	0	0	0	12	0	0	61	59658	26	40014	13	40000	13	40000	65	8576687	1	60021	60040	60040	53454	45	53772	40013	20	40000	20	110000	60040	60043	1	1	30021	10	9	10	10	30000	10	0	0	2	0	0	0	1890	2	17	2	2	59829	3	50000	10	60041	60041	60041	60041	60041
50024	60040	449	0	0	0	0	0	0	61	59696	26	40013	13	40000	13	40000	65	8576687	0	60021	60040	60043	53454	3	53769	40013	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	1890	2	17	2	2	59826	3	50000	10	60041	60041	60041	60044	60044
50024	60040	449	0	0	0	0	0	0	1114	59696	26	40013	13	40009	13	40000	65	8576725	0	60021	60040	60040	53454	3	53769	40013	20	40000	20	110000	60040	60043	1	1	30021	10	9	10	10	30000	10	0	0	0	0	6	0	1890	2	17	2	2	59826	3	50000	10	60266	60044	60096	60041	60041
50024	60040	449	0	0	0	0	0	0	636	59717	26	40013	13	40000	13	40000	65	8577118	1	60024	60150	60262	53454	45	53787	40615	20	40000	20	110000	60040	60040	1	1	30021	10	9	10	10	30000	10	0	0	0	1	108	0	1890	2	49	2	2	59829	3	50000	10	60041	60041	60041	60041	60041

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v4.8b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0042

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50204	40042	300	0	0	0	2	103	39687	26	40127	125	40003	125	40000	625	5692179	1	40023	40042	40042	33453	7	33743	40125	200	40007	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	299	0	0	0	3	61	39685	26	40127	125	40004	125	40000	625	5692424	0	40023	40042	40042	33453	6	33744	40125	200	40007	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1	1	1	1917	17	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	0	0	1	61	39685	26	40127	125	40002	125	40000	625	5693510	0	40023	40042	40042	33453	7	33744	40125	200	40007	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	0	0	2	61	39685	26	40128	125	40001	125	40000	625	5691797	0	40023	40042	40042	33453	7	33744	40125	200	40007	200	110036	40042	40042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	299	0	0	0	1	61	39685	26	40128	125	40003	125	40000	625	5692269	0	40023	40042	40042	33453	7	33743	40125	200	40007	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	0	0	3	61	39684	26	40127	125	40003	125	40000	625	5692152	1	40023	40042	40042	33453	7	33743	40125	200	40007	200	110036	40042	40042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1	1	1	1916	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	0	0	4	1417	39684	26	40126	125	40003	125	40000	625	5692179	1	40023	40042	40042	33453	7	33743	40125	200	40007	200	110036	40042	40042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	0	0	0	61	39687	26	40127	125	40003	125	40000	625	5691934	0	40023	40042	40042	33453	7	33743	40125	200	40007	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1	1	1	1916	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	0	0	2	61	39685	26	40127	125	40002	125	40000	625	5693436	0	40023	40042	40042	33453	7	33743	40125	200	40007	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1	1	1	1916	16	39881	25	50000	100	40043	40043	40043	40043	40043
50204	40042	300	0	0	0	0	61	39686	26	40125	125	40003	125	40000	625	5692089	0	40023	40042	40042	33453	6	33744	40125	200	40007	200	110020	40042	40042	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1	1	1	1917	16	39881	25	50000	100	40043	40043	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0042

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50024	40042	300	0	0	61	39685	26	40016	13	40001	13	40000	65	5693437	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	2	17	2	2	39871	3	50000	10	40043	40043	40043	40043	40043
50024	40042	300	0	2	768	39684	26	40013	13	40002	13	40000	65	5692682	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	2	17	2	2	39871	3	50000	10	40043	40043	40043	40043	40043
50024	40042	300	0	3	61	39687	26	40013	13	40003	13	40000	65	5692685	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	2	17	2	2	39871	3	50000	10	40043	40043	40043	40043	40043
50024	40042	300	0	3	61	39684	26	40016	13	40003	13	40000	65	5692296	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	2	17	2	2	39871	3	50000	10	40043	40043	40043	40043	40043
50024	40042	299	0	2	61	39685	26	40017	13	40001	13	40000	65	5693436	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	2	17	2	2	39871	3	50000	10	40043	40043	40043	40043	40043
50024	40042	300	0	1	61	39687	26	40014	13	40000	13	40000	65	5692269	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	2	17	2	2	39871	3	50000	10	40043	40043	40043	40043	40043
50024	40042	300	0	1	61	39684	26	40016	13	40002	13	40000	65	5692195	0	40023	40042	40042	33469	3	33771	40013	20	40000	22	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	2	17	2	2	39871	3	50000	10	40043	40043	40043	40043	40043
50024	40042	300	0	4	61	39684	26	40015	13	40002	13	40000	65	5692287	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	2	17	2	2	39871	3	50000	10	40043	40043	40043	40043	40043
50024	40042	300	0	0	61	39685	26	40014	13	40001	13	40000	65	5693436	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	2	17	2	2	39871	3	50000	10	40043	40043	40043	40043	40043
50024	40042	299	0	2	61	39684	26	40016	13	40003	13	40000	65	5692195	0	40023	40042	40042	33469	3	33771	40013	20	40000	20	110000	40042	40042	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	2	17	2	2	39871	3	50000	10	40043	40043	40043	40043	40043

Test 6: Latency 1->5

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v4.8b
  add v4.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50204	80038	600	0	0	12	103	79686	26	40125	125	40000	125	40000	625	11457640	0	0	80019	0	80038	80038	73428	7	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	6	1	1	1	1959	0	0	3	16	5	3	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	12	61	79686	26	40125	125	40000	125	40000	625	11457640	1	0	80019	0	80038	80038	73428	7	73740	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	0	0	2	16	4	3	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	12	61	79686	26	40125	125	40000	125	40000	625	11457640	1	0	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	4	0	1	1	1	1917	0	0	3	16	3	4	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	0	0	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	0	0	4	16	4	4	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	0	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	0	0	3	16	3	7	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	1	0	298	79686	26	40125	125	40000	125	40000	625	11457640	1	0	80019	3	80038	80038	73428	7	73740	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	0	0	3	16	3	3	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	0	0	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1917	0	0	1	16	3	3	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	600	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	0	80019	0	80038	80038	73428	7	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	9	1	1	1	1917	0	0	3	16	3	1	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	0	0	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	2	3	1	1	1	1917	0	0	4	16	4	3	79809	25	50000	100	80039	80039	80039	80039	80039
50204	80038	599	0	0	0	61	79686	26	40125	125	40000	125	40000	625	11457640	1	0	80019	0	80038	80038	73428	6	73741	40125	200	40007	200	110020	80038	80038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	1	1	1916	0	0	3	16	3	3	79809	25	50000	100	80039	80039	80039	80039	80039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
50024	80038	600	1	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	3	17	3	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	2	0	1890	3	17	3	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	4	17	3	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	3	17	3	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	3	17	3	3	79796	3	50000	10	80039	80039	80039	80194	80039
50024	80038	599	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	3	17	3	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	3	17	3	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	3	17	4	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	599	0	0	0	0	0	0	0	61	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	3	17	4	3	79796	3	50000	10	80039	80039	80039	80039	80039
50024	80038	600	0	0	0	0	0	0	0	726	79686	26	40013	13	40000	13	40000	65	11457640	0	80019	80038	80038	73443	0	3	73767	40013	20	40000	20	110000	80038	80038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	0	1890	3	17	3	3	79796	3	50000	10	80039	80039	80039	80039	80039

Test 7: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  movi v1.16b, 0
  tbx v1.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  movi v2.16b, 0
  tbx v2.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  movi v3.16b, 0
  tbx v3.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  movi v4.16b, 0
  tbx v4.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  movi v5.16b, 0
  tbx v5.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  movi v6.16b, 0
  tbx v6.8b, { v8.16b, v9.16b, v10.16b }, v11.8b
  movi v7.16b, 0
  tbx v7.8b, { v8.16b, v9.16b, v10.16b }, v11.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320204	60057	450	0	0	49115	520	0	26	240125	125	240000	125	240000	625	3299571	1	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	81469	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	5	16	1	1	60044	25	320000	100	60048	60048	60048	60048	60048
320204	60047	449	0	0	0	283	0	26	240125	125	240000	125	240000	625	3299571	1	60094	0	60047	60047	19973	0	3	41426	240125	200	240000	200	720000	60047	81400	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	60044	25	320000	100	60048	60048	81800	60048	60048
320204	60047	449	0	0	0	222	0	26	240125	125	240000	125	240000	625	3299571	1	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	1	0	10110	1	16	1	1	60044	25	320000	100	60048	60048	60048	60048	60048
320204	60047	449	0	0	0	201	0	26	240125	125	240000	125	240000	625	3299571	1	60028	0	81736	60047	19973	0	3	41321	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	60044	25	320000	100	60048	60048	60048	60048	81470
320204	60047	450	0	0	0	1916	0	26	240125	125	240000	125	240000	625	3299571	1	81405	0	60047	60047	41252	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	60044	25	320000	100	81349	60048	60048	81425	60048
320204	81302	450	0	0	0	180	0	26	240125	125	290632	125	240000	625	3299571	1	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	60044	25	320000	100	60048	60048	60048	60048	60048
320204	60047	450	0	0	0	1088	0	26	240125	125	240000	125	240000	625	3299571	0	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	60044	25	320000	100	60048	60048	81529	60048	60048
320204	81736	450	0	0	0	222	0	26	240125	125	240000	125	240000	625	3299571	0	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	60044	25	320000	100	81737	60048	60048	60048	60048
320204	80982	450	0	0	49553	1062	0	26	240125	125	289899	125	240000	625	3299571	0	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	60044	25	320000	100	60048	60048	60048	60048	60048
320204	60047	450	0	0	0	157	0	26	240125	125	240000	125	240000	640	11434683	1	60028	0	60047	60047	19973	0	3	20004	240125	200	240000	200	720000	60047	60047	1	1	160201	100	99	100	100	160000	100	0	0	3	10110	1	16	1	1	60044	25	320000	100	60048	60048	60048	60048	60048

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320024	60048	609	0	0	0	0	0	0	0	151	0	26	240013	13	240000	13	240000	65	3299571	1	0	5	60028	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	1	1	20	17	2	1	1	9	20	60044	3	15	7	320000	10	81179	60048	60048	60048	60048
320024	60047	450	0	0	0	0	0	0	0	164	0	26	240013	13	240000	13	240000	65	3299571	1	1	5	60028	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	4	1	19	17	2	1	1	20	20	60044	3	15	14	320000	10	60048	60048	60048	60048	60048
320024	60047	450	0	0	0	0	0	0	0	139	0	26	240013	13	240000	13	240000	65	3299571	1	1	5	60028	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	4	1	19	17	4	1	1	6	19	60044	3	30	9	320000	10	60048	60048	60048	60048	60048
320024	60047	450	0	0	0	0	0	0	0	160	0	26	240013	13	240000	13	240000	65	3299571	1	1	5	60028	81519	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	11	4	1	19	17	2	1	1	19	19	60044	3	15	7	320000	10	60048	60107	60048	60048	60048
320024	60047	450	0	0	0	0	0	0	0	1076	0	26	240013	13	240000	13	240000	65	3299571	1	1	5	60028	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	4	1	19	17	2	1	1	19	19	60044	3	15	7	320000	10	60048	60048	60048	60048	60048
320024	60047	450	0	0	0	0	0	0	0	629	0	26	240013	13	240000	13	240000	65	3299571	1	1	5	60028	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	4	1	19	17	2	1	1	6	19	60044	3	15	7	320000	10	60048	60048	60048	60048	60048
320024	60047	450	0	0	0	0	0	0	0	582	0	26	240013	13	240000	13	240000	65	3299571	1	1	5	60028	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	4	1	19	17	2	1	1	19	8	60044	3	15	7	320000	10	60048	60048	60048	60048	60048
320024	60047	449	0	0	0	0	0	0	0	958	0	26	240013	13	240000	13	240000	65	3299571	1	1	5	60028	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	4	1	19	17	2	1	1	19	8	60044	3	15	7	320000	10	60048	60048	60048	60048	81663
320024	60047	450	0	0	0	0	0	0	0	158	0	26	240096	13	240000	13	240000	65	3299571	1	1	5	60028	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	8	4	1	6	17	2	1	1	10	20	60044	5	15	7	320000	10	60048	60048	60048	60048	60048
320024	60047	450	0	0	0	0	0	0	0	674	57935	26	240013	13	240000	13	240000	65	3299571	1	1	5	60028	60047	60047	19996	0	3	20026	240013	20	240000	20	720000	60047	60047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	11	4	1	19	17	2	1	1	19	8	60044	3	15	7	320000	10	60048	60048	60048	81644	60048

TBX (three register table, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations