Firestorm: TBX (two register table, 16B) measurements

Code:

  tbx v0.16b, { v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
2004	4086	31	0	0	18	0	82	3687	25	2000	2000	2000	551680	0	4018	4087	4085	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	1	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	31	0	0	0	0	103	3687	44	2012	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3853	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	0	61	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	1	3843	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	0	61	3687	25	2000	2000	2000	551680	0	4018	4084	4086	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	0	61	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2152	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	249	0	61	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2152	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	31	0	0	0	0	61	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	0	61	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	33	0	84	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	192	0	251	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3787	2000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  tbx v0.16b, { v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	299	2	2	0	0	1	65	39687	25	20100	100	20000	100	20000	500	5717680	40018	40037	40037	37179	6	37491	20100	200	20008	200	60024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	2	0	0	0	1	1	1	718	0	3	16	4	3	39801	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	2	2	0	0	1	65	39687	25	20100	100	20000	100	20000	500	5717680	40018	40037	40037	37179	6	37491	20100	200	20008	200	60024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	5	16	4	3	39857	0	20000	100	40038	40232	40038	40038	40038
20204	40037	300	2	1	0	0	1	65	39687	25	20100	100	20048	100	20000	500	5717680	40018	40277	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	9	0	0	0	0	712	0	5	16	5	10	39787	0	20000	100	40038	40184	40038	40086	40038
20204	40037	300	1	1	0	0	1	65	39687	25	20100	100	20000	100	20000	500	5717680	40018	40037	40037	37172	3	37495	20406	202	20000	200	60000	40037	40232	1	1	10201	100	99	100	100	10000	100	0	3	0	0	0	0	0	0	712	0	6	16	6	6	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	1	1	0	12	1	107	39687	25	20100	100	20000	100	20000	500	5717680	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	712	0	7	16	6	6	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	1	1	0	219	1	730	39687	25	20100	104	20000	100	20000	500	5717680	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	712	0	6	16	5	5	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	1	1	0	0	1	65	39687	25	20100	100	20000	100	20000	500	5717680	40054	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	2	0	0	0	0	0	0	0	712	0	7	53	6	6	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	1	1	0	0	1	65	39687	25	20100	100	20000	100	20000	500	5717680	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	8166	0	0	0	0	712	0	6	16	6	4	39787	2	20000	100	40086	40038	40038	40038	40038
20204	40037	300	1	1	0	0	1	65	39687	25	20100	100	20000	100	20000	500	5717680	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	1	0	9	0	0	0	0	712	0	5	16	7	6	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	1	1	0	78	1	65	39687	25	20100	100	20000	100	20000	500	5717680	40018	40037	40037	37172	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	0	0	0	712	0	4	16	6	6	39787	0	20000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	0	7	16	3	3	39787	0	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	0	3	16	3	3	39787	0	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20660	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	0	3	16	3	3	39787	0	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	5466	39566	241	20070	10	20132	10	21672	50	5731480	1	40414	40558	40612	37211	49	37732	21682	20	20982	22	65442	40656	40572	12	1	10021	10	9	10	10	10000	10	4	0	2	0	1	0	22560	0	781	0	7	70	4	3	40195	0	20000	10	40622	40623	40327	40232	40086
20024	40085	299	0	0	0	0	0	0	0	5949	39632	243	20142	12	20144	12	21672	72	5731793	1	40450	40606	40617	37222	56	37745	21682	22	21968	22	65574	40617	40577	13	1	10021	10	9	10	10	10000	10	2	2	2	0	1	2	24483	2	857	0	8	133	7	7	40009	2	20000	10	40330	40622	40329	40427	40330
20024	40572	302	0	1	0	11	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	1	40414	40464	40232	37214	7	37686	21380	22	20980	20	64908	40230	40474	3	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	0	0	782	0	6	97	4	3	39972	0	20000	10	40281	40474	40426	40333	40475
20024	40267	304	0	0	1	10	7	540	880	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40450	40465	40621	37215	44	37572	21990	22	21640	20	66888	40525	40316	12	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	23980	0	847	0	6	132	5	9	40027	0	20000	10	40038	40038	40038	40038	40038
20024	40037	311	0	0	0	9	6	1716	792	61	39687	25	20144	10	20192	10	21520	83	5731793	0	40414	40465	40525	37224	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	2	4	0	2	0	0	0	0	640	0	3	16	3	4	39787	0	20000	10	40038	40038	40038	40038	40038
20024	40037	311	0	0	0	0	0	3	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40065	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	3	0	640	0	3	16	3	3	39787	0	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	0	0	0	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	0	40018	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	0	3	16	3	3	39787	0	20000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b }, v3.16b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	60038	449	1	0	1	0	0	0	546	528	145	59687	26	30125	125	30000	125	30000	625	8587627	0	60019	0	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	449	0	0	0	0	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	0	60019	0	60139	60246	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	3	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	0	453	0	61	59687	26	30125	125	30000	125	30000	625	8587627	0	60019	0	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	0	60019	0	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	0	1910	2	16	1	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	0	60019	0	60038	60038	54671	0	3	54995	30125	200	30000	200	81770	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	50	2	0	0	0	0	0	1938	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	451	0	1	0	0	0	0	0	0	61	59667	26	30125	125	30000	125	30000	625	8587627	0	60019	3	60038	60038	54671	0	12	55040	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	0	0	0	61	59687	165	30164	125	30000	125	30000	625	8587627	0	60056	0	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	2	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	449	0	0	0	0	0	0	3	0	61	59687	53	30125	125	30000	125	30000	625	8595049	0	60019	0	60038	60038	54653	0	3	54995	30125	202	30000	200	80000	60038	60038	1	1	30202	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	0	1910	2	16	6	2	59801	25	40000	100	60095	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	0	0	0	61	59687	161	30125	125	30000	125	30000	625	8587627	0	60019	3	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	7	1	30202	100	99	100	100	30000	100	0	0	0	0	7	0	0	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60350	60039	60039
40204	60038	450	0	0	0	0	6	0	0	0	61	59687	26	30125	125	30000	130	30000	625	8587627	0	60019	0	60038	60038	54671	0	3	54995	30278	206	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	3	2	1	4	12343	0	0	0	0	1910	2	16	2	3	59801	25	40000	100	60039	60039	60039	60039	60039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	60038	450	0	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	3	0	0	1890	0	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	449	0	0	0	0	681	0	0	726	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	7	0	15	0	0	1890	0	3	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60299	449	0	0	0	0	0	0	0	103	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	231	0	0	1890	0	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	0	251	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	6	0	0	1890	0	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	449	0	0	0	0	0	0	0	61	59678	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60092	54691	0	3	55017	30013	20	30000	20	80000	60038	60350	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	18	0	0	1890	0	2	17	2	3	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	0	3	55112	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	3	0	0	1890	0	2	17	2	2	59801	3	40000	10	60142	60092	60039	60039	60039
40024	60038	449	0	0	0	0	0	0	0	147	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	93	0	0	1890	0	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	449	0	0	0	0	0	0	2	61	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	1	0	213	0	0	1890	0	2	17	2	5	59801	3	40000	10	60039	60039	60093	60039	60039
40024	60038	450	0	1	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	219	0	0	1890	0	3	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	225	0	0	1890	0	3	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b }, v3.16b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	40043	300	0	1	1	2	0	0	1	284	39659	83	30213	125	30083	125	30000	642	5700933	0	40021	40040	40070	34731	0	3	35042	30125	200	30000	200	80000	40040	40040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	2	16	2	2	39844	25	40000	100	40044	40041	40041	40101	40044
40204	40070	299	0	0	0	0	0	0	0	84	39707	26	30126	125	30002	125	30000	625	5701226	1	40024	40043	40040	34685	0	3	34997	30125	200	30000	200	80000	40043	40040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	2	16	2	2	39844	29	40000	100	40041	40041	40041	40041	40041
40204	40040	300	0	0	0	0	0	0	2	254	39707	26	30127	125	30002	125	30000	625	5700760	0	40024	40043	40040	34716	0	3	34997	30125	200	30000	200	80000	40040	40043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	2	16	2	2	39844	25	40000	100	40041	40041	40041	40041	40086
40204	40040	299	0	0	0	0	0	0	1	61	39699	26	30135	125	30000	125	30000	625	5700933	1	40021	40040	40040	34685	0	3	35000	30125	200	30000	200	80000	40043	40043	1	1	30201	100	99	100	100	30000	100	0	3	0	0	1910	2	16	2	2	39844	25	40000	100	40041	40041	40041	40041	40041
40204	40040	300	0	0	0	0	0	0	1	1012	39699	26	30127	125	30002	125	30000	625	5700933	0	40021	40040	40040	34685	0	3	34997	30125	200	30000	200	80000	40043	40040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	2	16	2	2	39844	25	40000	100	40044	40041	40041	40041	40041
40204	40085	300	0	0	0	0	0	0	1	165	39707	26	30126	125	30000	125	30000	625	5700760	0	40066	40040	40040	34685	0	3	35000	30125	200	30000	200	81264	40040	40040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	2	16	2	2	39844	25	40000	100	40041	40071	40086	40071	40041
40204	40040	300	0	0	0	0	0	0	0	61	39699	26	30127	125	30000	125	30000	625	5700305	0	40021	40043	40040	34685	7	3	35000	30125	200	30000	200	80000	40085	40040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	2	16	2	2	39874	25	40000	100	40086	40044	40044	40041	40074
40204	40040	300	0	0	0	0	0	0	1	61	39699	26	30125	125	30000	125	30000	625	5700933	0	40021	40040	40040	34685	0	3	34997	30125	200	30000	200	80000	40040	40040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	2	16	2	2	39844	25	40000	100	40041	40044	40041	40047	40041
40204	40040	300	0	0	0	0	222	0	0	251	39707	26	30135	125	30010	125	30000	625	5700933	1	40021	40043	40070	34688	0	3	34997	30125	200	30000	200	80000	40070	40070	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	2	16	2	2	39844	25	40000	100	40041	40041	40041	40041	40041
40204	40040	300	0	0	0	0	0	0	0	89	39699	26	30126	125	30000	125	30000	625	5700933	0	40021	40040	40043	34685	0	3	34997	30125	200	30000	200	80000	40040	40043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	2	16	2	2	39889	25	40000	100	40041	40041	40044	40041	40044

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	40040	300	0	0	61	39707	54	30049	13	30001	13	30000	65	5700305	1	40021	0	40043	40040	34708	3	35019	30013	20	30000	20	80000	40085	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	4	17	3	3	39846	3	40000	10	40041	40041	40041	40041	40041
40024	40040	300	132	0	61	39707	26	30013	13	30000	13	30000	65	5700933	1	40021	0	40040	40040	34708	3	35019	30013	20	30000	20	80000	40043	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	3	17	3	3	39846	3	40000	10	40041	40041	40041	40041	40044
40024	40043	300	0	1	61	39707	26	30013	13	30000	13	30000	65	5700933	1	40021	0	40040	40043	34708	3	35025	30013	20	30000	20	80000	40040	40040	1	1	30021	10	9	10	10	30000	10	1	0	0	1890	3	17	3	3	39843	3	40000	10	40044	40044	40041	40044	40047
40024	40040	300	0	0	128	39710	26	30013	13	30001	13	30000	65	5701300	1	40021	0	40040	40040	34708	3	35019	30013	20	30000	20	80000	40040	40043	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	3	17	4	3	39843	3	40000	10	40044	40041	40041	40041	40041
40024	40043	299	0	0	61	39707	26	30049	13	30000	13	30000	65	5700933	1	40021	0	40040	40040	34708	3	35019	30013	20	30000	20	80000	40040	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	3	17	3	3	39843	3	40000	10	40041	40044	40041	40041	40041
40024	40046	300	0	10	61	39710	26	30013	13	30000	13	30000	65	5701226	0	40021	0	40043	40043	34708	3	35049	30013	20	30000	20	80000	40040	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	3	17	3	3	39846	3	40000	10	40047	40041	40044	40044	40044
40024	40046	300	0	0	214	39707	26	30013	13	30000	13	30000	65	5704752	1	40021	0	40040	40040	34711	3	35022	30013	20	30000	20	80000	40040	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	3	17	4	3	39843	3	40000	10	40041	40041	40071	40044	40044
40024	40040	299	0	0	105	39707	26	30013	13	30000	13	30000	65	5700933	0	40021	0	40046	40040	34711	3	35019	30013	20	30000	20	80000	40040	40085	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	3	17	3	4	39843	3	40000	10	40041	40041	40041	40041	40041
40024	40040	300	0	0	174	39707	26	30013	13	30010	13	30000	65	5701226	0	40021	0	40040	40040	34711	3	35025	30013	20	30000	20	80000	40040	40043	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	4	17	3	3	39843	3	40000	10	40044	40044	40041	40041	40044
40024	40043	300	0	2	61	39707	26	30013	13	30001	13	30000	65	5700933	0	40021	0	40040	40040	34708	3	35019	30013	20	30000	20	80000	40040	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	3	17	3	3	39843	3	40000	10	40041	40041	40041	40041	40044

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b }, v3.16b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	60038	449	1	1	0	2	64	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1912	5	16	5	5	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	1	1	0	1	254	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1912	5	16	5	6	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	449	1	1	0	1	152	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	21	0	1912	5	16	3	5	59801	25	40000	100	60039	60039	60039	60090	60039
40204	60038	450	1	1	0	1	64	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	9	0	1912	6	16	5	5	59949	25	40000	100	60039	60039	60039	60039	60039
40204	60091	451	1	1	0	1	64	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1913	4	16	4	4	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	1	1	12	1	64	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	0	3	54995	30125	200	30000	204	80000	60038	60091	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1913	6	50	5	3	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	1	1	12	1	64	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	2	4	0	0	4	4056	0	1912	4	16	7	8	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	1	1	0	1	64	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1912	5	16	3	5	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	449	1	1	0	1	1003	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	1	0	0	0	1912	5	16	5	5	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	451	1	1	0	1	64	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	1913	6	16	5	3	59801	25	40000	100	60039	60039	60039	60039	60039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	60038	450	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	7	17	7	7	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	4	17	4	7	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	118	59687	26	30013	13	30012	13	30000	65	8587627	1	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	4	17	4	7	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	4	17	4	7	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	6	0	1890	7	17	7	7	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	251	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	7	17	7	5	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	449	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80880	60089	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	4	17	7	4	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	449	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54690	0	3	55017	30013	20	30168	20	80000	60140	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	1890	7	17	7	4	59801	3	40000	10	60196	60039	60039	60039	60039
40024	60139	450	0	132	1266	59687	26	30013	13	30000	13	30000	81	8588904	0	60093	0	60038	60038	54687	0	3	55017	30013	20	30000	20	80000	60090	60038	1	1	30021	10	9	10	10	30000	10	2	7	5270	1890	7	17	7	4	59801	3	40000	10	60089	60039	60039	60039	60039
40024	60038	450	0	180	221	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	0	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	1	0	1890	7	17	7	4	59801	3	40000	10	60039	60039	60039	60039	60039

Test 6: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.16b, { v8.16b, v9.16b }, v10.16b
  movi v1.16b, 0
  tbx v1.16b, { v8.16b, v9.16b }, v10.16b
  movi v2.16b, 0
  tbx v2.16b, { v8.16b, v9.16b }, v10.16b
  movi v3.16b, 0
  tbx v3.16b, { v8.16b, v9.16b }, v10.16b
  movi v4.16b, 0
  tbx v4.16b, { v8.16b, v9.16b }, v10.16b
  movi v5.16b, 0
  tbx v5.16b, { v8.16b, v9.16b }, v10.16b
  movi v6.16b, 0
  tbx v6.16b, { v8.16b, v9.16b }, v10.16b
  movi v7.16b, 0
  tbx v7.16b, { v8.16b, v9.16b }, v10.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240204	40065	644	0	0	0	326	0	26	160125	125	160000	125	160000	650	1599960	0	0	40070	40043	40043	9973	0	3	55557	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	297	0	1	1	40040	6	240000	100	40413	40165	86884	40044	40044
240204	40043	300	0	0	0	67	0	26	160125	125	160000	125	160000	650	1599960	0	0	40024	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	0	1	1	40040	25	240000	100	40044	40044	40044	40044	40044
240204	40043	300	0	0	0	153	0	26	160125	125	160000	125	160000	650	1599960	0	1	40024	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	0	1	1	40040	25	240000	100	40044	40044	40044	40044	40044
240204	40043	300	0	0	0	109	0	26	160125	125	160000	125	160000	650	1599960	0	1	40024	40043	40043	9973	8807	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	0	1	1	40040	25	240000	100	40044	40044	40111	40044	87213
240204	40043	651	0	0	0	86	0	26	160125	125	160000	125	160000	650	1599960	0	1	40024	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	0	1	1	40040	25	240000	100	40044	40044	40044	40044	40044
240204	40043	300	0	0	0	90	0	26	160125	125	160000	125	160000	650	1599960	0	1	40024	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	0	1	1	40040	25	240000	100	40044	40044	40044	40044	40044
240204	40043	299	0	0	0	67	0	26	160125	125	160000	125	160000	650	1599960	0	1	40024	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	0	1	1	40040	25	240000	100	40044	40044	40044	40044	40044
240204	40043	300	0	0	0	817	0	26	160125	125	160000	125	160000	650	1599960	0	1	40024	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	0	1	1	40040	25	240000	100	40044	40044	40044	40044	40044
240204	40043	300	0	0	0	1379	0	26	160125	125	160000	125	160000	650	1599960	0	1	85650	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	0	1	1	40040	25	240000	100	40044	40044	40044	40044	40044
240204	40043	300	0	0	0	107	0	26	160125	125	160000	125	160000	650	1599960	0	1	40024	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	85673	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	0	1	1	40040	25	240000	100	40044	40044	40044	40044	40044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240024	40043	300	0	0	0	0	0	0	0	175	0	26	160013	13	160000	13	160000	68	1599960	1	1	40024	40043	40043	9996	0	3	10022	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	19	17	2	1	1	5	15	40040	3	15	2	240000	10	40044	40044	40044	40044	40044
240024	40043	300	0	0	0	0	0	0	0	286	0	26	160013	13	277579	13	160000	68	1599960	1	1	40024	40043	40043	9996	0	3	10022	160013	20	160000	20	480000	86367	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	14	17	2	1	1	15	7	40040	3	15	2	240000	10	40044	40044	40044	40044	40044
240024	40043	300	0	0	0	0	0	116167	0	514	0	26	160013	13	160000	13	160000	68	1599960	1	1	40024	40043	40043	49363	0	3	10022	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	2	0	0	3	10024	3	2	2	4	17	2	2	1	15	10	40040	3	15	15	240000	10	40044	40163	40044	40044	40044
240024	40111	300	1	1	3	0	192	0	0	133	0	26	160013	13	160000	13	160000	68	1599960	1	1	40024	40043	40043	9996	8985	3	10022	160013	20	160000	20	480000	84678	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	5	17	2	2	1	6	9	40040	3	30	4	240000	10	40044	40044	40044	40044	40044
240024	40043	300	0	0	0	0	0	0	0	154	0	26	160013	13	160000	13	160000	68	12043078	0	1	40024	88092	40043	48526	0	3	10022	160013	20	160000	20	480000	40043	87071	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	9	17	4	2	1	5	12	40040	3	15	2	240000	10	87228	40044	40044	40044	40044
240024	40043	659	0	0	0	0	0	0	0	346	0	26	160013	13	160000	13	160000	68	1599960	0	1	40024	40043	40043	9996	0	3	10022	160013	20	160000	20	480000	86093	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10022	3	2	1	8	17	4	1	1	14	9	40040	3	15	2	240000	10	40044	40044	40044	40044	40044
240024	40043	300	0	0	0	0	0	0	0	49	0	26	160013	13	160000	13	160000	68	1599960	0	1	40024	40043	40043	9996	0	37	10043	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	3	1	1	10	17	2	2	1	10	9	40040	3	15	2	240000	10	40044	40044	40044	40044	40044
240024	86367	647	0	0	0	12	0	0	0	137	0	47	160115	11	160000	13	160000	68	1600968	1	1	40024	40043	40109	47842	8972	3	10022	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	2	3	10022	3	1	1	9	17	2	1	1	11	6	40040	3	15	2	240000	10	40044	40044	40044	40044	40044
240024	40043	300	0	0	0	0	0	0	0	49	0	26	160013	13	160000	13	160000	66	1599960	1	1	40024	86093	40043	9996	0	3	56346	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10022	3	1	1	14	17	2	1	1	10	9	40040	3	15	2	240000	10	40044	40044	40044	40044	40044
240024	40043	299	0	0	0	12	0	0	0	49	0	26	160013	13	160000	13	160000	68	11685514	1	1	40024	88092	40043	9996	0	3	10022	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	3	0	10022	3	1	1	5	17	2	1	1	8	10	40040	3	15	2	240000	10	40044	40044	40044	40044	40044

TBX (two register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations