Firestorm: TBX (two register table, 8B) measurements

Code:

  tbx v0.8b, { v1.16b, v2.16b }, v3.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
2004	4037	31	0	0	0	156	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	73	3	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	31	0	0	0	61	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	31	0	0	0	251	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	1	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	0	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	31	0	0	0	61	3687	25	2000	2000	2000	551680	1	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038
2004	4037	30	0	0	0	61	3687	25	2000	2000	2000	551680	1	4018	4037	4037	3447	3	3770	2000	2000	6000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3787	2000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  tbx v0.8b, { v1.16b, v2.16b }, v3.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	40037	300	84	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	0	40037	40037	37172	0	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	0	40037	40037	37172	0	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	39825	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	0	40037	40037	37172	0	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	0	40037	40037	37172	0	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	726	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	0	40037	40037	37172	0	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	712	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	0	40037	40037	37172	0	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	299	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	0	40037	40037	37172	0	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	89	39687	25	20100	100	20000	100	20000	500	5717680	1	40018	0	40037	40037	37172	0	3	37495	20100	200	20000	202	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	299	6	0	82	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	0	40037	40037	37172	0	3	37495	20100	200	20000	200	60504	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038
20204	40037	300	0	0	61	39687	25	20100	100	20000	100	20000	500	5717680	0	40018	0	40037	40037	37172	0	3	37495	20100	200	20000	200	60000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39787	0	20000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	40037	300	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	0	40037	40037	37205	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39687	46	20010	10	20000	10	20000	50	5717680	40018	0	40037	40037	37194	7	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	299	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	2	2	39787	20000	10	40038	40038	40038	40038	40038
20024	40037	300	0	0	61	39687	25	20010	10	20000	10	20000	50	5717680	40018	0	40037	40037	37194	3	37517	20010	20	20000	20	60000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39787	20000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b }, v3.8b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	60090	450	1	0	0	0	141	176	0	1056	59687	72	30125	125	30000	125	30000	625	8587627	1	60091	0	60140	60038	54668	0	3	54995	30125	200	30162	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	4	0	0	0	0	0	0	0	0	0	0	1939	2	25	2	2	59801	25	40000	100	60039	60039	60039	60091	60141
40204	60038	449	0	0	2	0	0	0	0	124	59687	26	30125	125	30000	125	30000	625	8588904	1	60019	0	60448	60090	54648	0	3	54995	30125	202	30331	200	81778	60454	60503	10	1	30201	100	99	100	100	30000	100	0	0	0	0	1	0	0	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	449	0	0	0	0	0	0	0	441	59687	26	30125	125	30000	125	30000	625	8587627	0	60019	0	60038	60038	54671	0	3	54995	31047	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	1	60019	0	60038	60038	54671	0	20	55025	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	2	0	1	0	4185	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	1	60019	0	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60090	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	3	0	0	0	0	1916	2	16	2	2	59832	25	40000	100	60039	60039	60039	60039	60091
40204	60038	450	0	1	0	0	507	104	0	94	59687	26	30125	125	30000	125	30000	625	8587627	1	60019	0	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60095	60039
40204	60038	450	0	0	0	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	1	60019	0	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	0	0	82	59687	26	30125	125	30000	125	30000	625	8587627	1	60019	0	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	3	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	449	0	0	0	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	1	60019	0	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	449	0	0	0	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	1	60019	0	60038	60038	54671	0	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	0	0	1910	2	16	2	2	59801	25	40000	100	60039	60039	60039	60039	60039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	60038	450	0	0	0	0	0	0	0	0	0	61	59687	48	30013	13	30012	13	30608	65	8587627	0	0	60164	60038	60038	54690	3	55017	30013	20	30000	20	80000	60242	60141	1	1	30021	10	9	10	10	30000	10	4	4	0	0	4	0	0	0	1890	0	7	17	3	3	59801	3	40000	10	60039	60191	60090	60039	60090
40024	60038	450	0	0	0	0	0	0	0	0	0	251	59687	26	30013	13	30000	13	30000	65	8587627	0	0	60019	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	3	17	3	3	59801	3	40000	10	60039	60039	60039	60039	60141
40024	60398	452	0	0	0	0	1	1	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8588904	0	0	60091	60038	60038	54693	3	55017	30013	20	30164	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	2	2	0	0	0	0	0	0	1890	0	3	17	3	3	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	0	60093	60089	60038	54691	11	55017	30165	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	2	0	0	1	0	0	0	0	1890	0	7	17	3	4	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	449	0	0	0	0	0	0	0	0	0	103	59687	26	30013	13	30000	13	30133	65	8587627	0	1	60019	60038	60038	54693	3	55032	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	3	17	3	3	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	0	60019	60038	60038	54688	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	3	2	0	0	0	1890	0	3	17	3	3	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	6	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	0	60019	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	3	17	3	4	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	1	60019	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	3	17	3	3	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	0	60019	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	3	17	7	3	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	0	60019	60038	60038	54700	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	0	3	17	3	7	59801	3	40000	10	60039	60039	60039	60039	60039

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b }, v3.8b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0043

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	40040	299	0	12	0	61	39682	26	30135	125	30002	125	30000	625	5700933	0	40024	40043	40040	34689	3	34997	30125	200	30000	200	80000	40040	40043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	0	0	0	0	1910	1	16	1	1	39844	25	40000	100	40044	40041	40044	40041	40044
40204	40070	310	0	3	1	729	39706	26	30125	125	30001	125	30000	625	5704752	0	40021	40043	40040	34692	6	34996	30125	200	30006	200	80016	40040	40040	2	1	30201	100	99	100	100	30000	100	0	0	0	0	0	216	1	1	1	1917	0	16	0	0	39854	25	40000	100	40041	40041	40041	40041	40041
40204	40046	300	0	0	0	61	39722	26	30125	125	30000	125	30000	625	5701226	0	40021	40040	40043	34695	7	34995	30125	200	30006	200	80016	40040	40040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	129	1	1	1	1918	0	16	0	0	39852	25	40000	100	40047	40041	40041	40041	40041
40204	40043	300	0	0	2	61	39707	26	30125	125	30000	125	30000	625	5704138	0	40051	40040	40040	34738	7	34996	30125	200	30006	200	80016	40085	40085	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	3995	0	0	0	1910	1	16	1	1	39847	25	40000	100	40041	40044	40041	40041	40041
40204	40040	300	0	0	2	61	39732	26	30126	125	30001	125	30000	625	5707839	0	40051	40043	40043	34685	3	34997	30125	200	30000	200	80000	40070	40040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	21	0	0	0	1910	1	16	1	1	39874	25	40000	100	40041	40044	40044	40041	40047
40204	40043	300	0	0	11	61	39732	26	30161	125	30036	125	30000	625	5700933	0	40024	40043	40040	34691	3	34997	30125	200	30000	200	80000	40043	40040	1	1	30201	100	99	100	100	30000	100	0	0	0	1	0	21	0	0	0	1910	1	16	1	1	39897	25	40000	100	40041	40041	40071	40071	40086
40204	40043	315	0	0	0	61	39707	26	30161	125	30001	125	30000	625	5707839	0	40066	40040	40040	34689	3	35003	30125	200	30000	200	80000	40040	40040	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	36	0	0	0	1910	1	16	1	1	39847	25	40000	100	40071	40041	40044	40044	40041
40204	40040	300	0	0	2	61	39732	26	30125	125	30002	125	30000	625	5701151	0	40021	40040	40040	34691	3	35042	30125	200	30000	200	80000	40043	40043	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	129	0	0	0	1910	1	16	1	1	39844	25	40000	100	40047	40071	40041	40044	40041
40204	40043	299	0	0	36	61	39722	26	30125	125	30002	125	30000	625	5704752	0	40066	40040	40040	34716	3	35042	30125	200	30000	200	80000	40043	40043	1	1	30201	100	99	100	100	30000	100	0	0	0	1	0	24	0	0	0	1910	1	16	1	1	39847	25	40000	100	40044	40044	40041	40041	40044
40204	40043	300	0	0	36	726	39732	26	30135	125	30000	125	30000	625	5700933	0	40021	40043	40040	34685	3	34997	30125	200	30000	200	80000	40040	40085	1	1	30201	100	99	100	100	30000	100	0	0	0	0	0	126	0	0	0	1910	1	16	1	1	39847	25	40000	100	40041	40044	40041	40041	40047

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bc	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	40043	299	0	0	0	0	1	61	39707	26	30049	13	30000	13	30000	65	5700933	1	40021	40040	40040	34708	3	35019	30013	20	30000	20	80000	40046	40043	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	3	17	3	3	39843	3	40000	10	40041	40044	40086	40041	40041
40024	40040	300	0	0	0	0	2	61	39707	26	30014	13	30036	13	30000	65	5704752	0	40021	40040	40101	34695	3	35019	30013	20	30000	20	80000	40040	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	5	17	5	3	39843	3	40000	10	40044	40041	40047	40044	40041
40024	40040	300	0	0	0	0	0	61	39707	26	30049	13	30000	13	30000	65	5701300	0	40021	40043	40040	34708	3	35052	30013	20	30000	20	80000	40040	40085	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	2	17	5	3	39888	3	40000	10	40044	40041	40086	40047	40047
40024	40040	300	0	0	0	0	0	61	39707	26	30013	13	30001	13	30000	65	5704752	0	40066	40040	40040	34708	3	35019	30013	20	30000	20	80000	40040	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	4	17	4	4	39888	3	40000	10	40044	40044	40086	40041	40044
40024	40085	300	0	0	0	0	0	61	39707	26	30014	13	30001	13	30000	65	5701548	0	40066	40043	40043	34708	3	35022	30013	20	30000	20	80000	40040	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	4	17	5	4	39843	3	40000	10	40041	40041	40041	40041	40041
40024	40040	300	0	0	0	0	0	61	39732	26	30013	13	30036	13	30000	65	5700933	0	40021	40040	40043	34708	3	35019	30013	20	30243	20	80000	40043	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	3	17	3	3	39846	3	40000	10	40041	40086	40044	40086	40041
40024	40040	311	0	0	21	0	0	300	39732	26	30049	13	30001	13	30000	65	5700305	0	40027	40085	40040	34708	3	35019	30013	20	30000	20	80000	40040	40040	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	4	17	3	3	39888	3	40000	10	40086	40044	40041	40086	40041
40024	40040	299	0	0	0	0	1	726	39707	26	30013	13	30036	13	30000	65	5705152	0	40021	40040	40040	34753	3	35022	30013	20	30000	20	80000	40040	40040	1	1	30021	10	9	10	10	30000	10	0	0	1	0	0	1890	6	17	4	4	39843	3	40000	10	40041	40044	40041	40041	40041
40024	40043	300	1	0	0	0	36	61	39710	26	30013	13	30000	13	30000	65	5700305	1	40021	40040	40040	34708	3	35019	30013	20	30000	20	80000	40085	40046	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	4	17	4	5	39843	3	40000	10	40041	40044	40041	40041	40086
40024	40040	300	0	0	0	0	1	61	39707	26	30013	13	30002	13	30000	65	5700760	0	40021	40073	40040	34738	3	35019	30013	20	30000	20	80000	40046	40043	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	1890	2	17	4	3	39846	3	40000	10	40086	40041	40044	40041	40041

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b }, v3.8b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40204	60245	450	0	0	0	0	0	2193	59687	49	30125	127	30000	125	30000	625	8587627	60019	60038	60038	54671	36	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	16	1	1	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	0	0	1910	1	16	1	1	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	98	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	2	0	0	1910	1	16	1	1	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	12	1	103	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	3	3	1910	1	16	1	1	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	449	0	0	0	54	0	61	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	3	0	1910	1	16	1	1	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	61	59687	26	30166	125	30000	125	30000	625	8587627	60019	60038	60038	54671	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	30	0	1910	1	51	1	1	59801	25	40000	100	60039	60095	60039	60039	60039
40204	60038	450	1	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	3	0	1910	1	16	1	1	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	103	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	3	54995	30125	200	30166	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	5	3	1910	1	16	1	1	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	61	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	1	9	1910	1	16	1	1	59801	25	40000	100	60039	60039	60039	60039	60039
40204	60038	450	0	0	0	0	0	3057	59687	26	30125	125	30000	125	30000	625	8587627	60019	60038	60038	54671	3	54995	30125	200	30000	200	80000	60038	60038	1	1	30201	100	99	100	100	30000	100	0	0	3	0	1910	1	16	1	1	59949	25	40000	100	60039	60039	60039	60039	60039

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
40024	60038	450	0	0	0	0	12	0	103	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	108	0	0	1890	3	26	2	2	59877	3	40000	10	60143	60039	60145	60039	60039
40024	60086	450	0	1	0	0	12	0	103	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	129	0	0	1890	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	103	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	81	3	0	0	1890	3	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	50	0	0	0	1890	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	449	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	3	55033	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	449	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	3	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	92	9	0	0	1890	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	1	60019	0	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	450	0	0	0	0	0	0	61	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	0	0	0	1890	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039
40024	60038	449	0	0	0	0	0	0	726	59687	26	30013	13	30000	13	30000	65	8587627	0	60019	0	60038	60038	54693	3	55017	30013	20	30000	20	80000	60038	60038	1	1	30021	10	9	10	10	30000	10	0	0	0	0	0	6	0	0	1890	2	17	2	2	59801	3	40000	10	60039	60039	60039	60039	60039

Test 6: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.8b, { v8.16b, v9.16b }, v10.8b
  movi v1.16b, 0
  tbx v1.8b, { v8.16b, v9.16b }, v10.8b
  movi v2.16b, 0
  tbx v2.8b, { v8.16b, v9.16b }, v10.8b
  movi v3.16b, 0
  tbx v3.8b, { v8.16b, v9.16b }, v10.8b
  movi v4.16b, 0
  tbx v4.8b, { v8.16b, v9.16b }, v10.8b
  movi v5.16b, 0
  tbx v5.8b, { v8.16b, v9.16b }, v10.8b
  movi v6.16b, 0
  tbx v6.8b, { v8.16b, v9.16b }, v10.8b
  movi v7.16b, 0
  tbx v7.8b, { v8.16b, v9.16b }, v10.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240204	40065	300	0	0	0	0	114580	3700	0	26	160125	125	160000	125	160000	650	1599960	1	40024	0	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	3	0	0	10110	1	16	1	1	40040	25	240000	100	40044	40044	40044	86391	40044
240204	40043	300	0	0	0	0	115723	61	0	26	160125	125	275723	125	160000	650	1599960	1	40024	0	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40276	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	10110	1	16	1	1	40040	25	240000	100	40044	40044	40044	40044	40044
240204	40043	300	0	0	0	0	0	44	0	26	160125	125	160000	125	160000	650	1599960	1	40024	0	40043	86390	9973	0	3	10000	160125	200	160000	200	480000	86433	87877	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40040	25	240000	100	40044	40044	40044	40044	40044
240204	87877	300	0	0	0	0	0	67	78090	26	160125	125	160000	125	160000	650	1599960	1	40024	0	40043	86390	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	2	40144	16	240000	100	40161	40158	40160	40168	40102
240204	40158	301	1	0	0	0	0	282	0	67	160212	125	160000	125	160000	650	11865787	1	87856	0	40208	40106	9973	0	3	10000	160125	200	160226	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	1	3	0	0	10110	1	16	1	1	40040	25	240000	100	40044	40044	40044	40044	40044
240204	87877	300	0	0	0	0	0	44	0	26	275848	125	160000	125	160000	650	1599960	1	40024	0	87877	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	86268	25	240000	100	40044	40044	40044	40044	40044
240204	40043	300	0	0	0	0	0	44	0	26	160125	125	160000	125	160000	650	1599960	1	40024	0	40043	40043	9977	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	1	0	0	0	10110	1	16	1	1	40040	25	240000	100	40044	40044	86391	40044	86391
240204	40043	300	0	0	0	0	0	65	0	26	160125	125	160000	125	160000	650	1599960	1	40024	0	40043	40043	9973	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	10110	1	16	1	1	40040	25	240000	100	40044	40044	40044	40044	60230
240204	85851	300	0	0	0	0	0	44	0	26	160125	125	160000	125	160000	650	1599960	0	40024	0	40043	40043	9973	0	3	10329	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	85501	25	240000	100	40044	40111	85687	40044	40044
240204	72740	300	0	0	0	0	115763	44	0	26	160125	125	160000	125	160000	650	1599960	1	40024	0	87147	40043	48214	0	3	10000	160125	200	160000	200	480000	40043	40043	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40040	25	240000	100	40044	40044	40044	86139	40044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240024	40043	642	0	0	0	0	0	0	0	0	49	75586	26	160013	13	160000	13	160000	68	1599960	1	1	5	40024	0	40043	40043	9996	0	3	10022	160013	20	160000	20	481320	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	1	28	18	17	2	1	1	11	17	40040	3	15	2	240000	10	40044	40044	40044	40044	40044
240024	40043	646	0	0	0	0	0	0	0	0	49	0	26	160013	13	160000	13	160000	68	1599960	1	1	5	40024	0	40043	40043	9996	0	3	10022	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10021	8	3	22	16	17	2	1	1	15	17	40040	3	15	14	240000	10	40044	40044	86249	40044	40044
240024	40043	300	0	0	0	0	0	0	0	0	714	0	26	160013	13	160000	13	160000	68	1599960	1	1	5	40024	0	40043	40043	9996	0	3	10022	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	11	4	18	16	17	4	2	2	15	15	40040	3	30	4	240000	10	40044	40044	40044	40044	40044
240024	40043	300	0	0	0	0	0	0	0	0	55	0	26	160013	13	160000	13	160000	68	1599960	1	1	5	40024	0	40043	40043	9996	0	3	10022	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	8	5	18	9	17	4	1	2	8	16	40040	3	30	2	240000	10	40044	40044	40044	40044	40044
240024	40043	300	0	0	0	0	0	0	0	0	49	0	26	160013	13	160000	13	160000	68	1599960	1	1	5	86216	0	40043	40043	9996	0	3	10022	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	9	0	10021	8	5	22	13	17	4	2	2	14	14	40040	3	15	2	240000	10	40044	85545	40044	40044	40044
240024	40043	300	0	0	0	0	0	0	0	0	49	0	26	160013	13	160000	13	160000	68	11707697	0	1	5	40024	0	40043	40043	9996	0	3	10022	160013	20	160000	20	480000	88560	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	11	5	16	15	17	2	1	1	16	17	40040	3	15	14	240000	10	40044	40044	40044	40044	40044
240024	40043	300	0	0	0	0	0	0	0	115203	49	0	26	160013	13	160000	13	160000	68	1599960	1	1	5	40024	3	40043	40043	48558	7656	3	10022	160013	20	160000	20	480000	40043	86248	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	11	5	23	14	17	2	1	1	17	15	40040	3	15	2	240000	10	40044	40044	40044	40044	40044
240024	40043	300	0	0	0	0	0	0	0	114073	49	0	26	160013	13	160000	13	160000	67	1599960	1	1	5	40024	0	86580	40043	9996	0	3	10022	160013	20	160000	20	480000	40043	85108	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10021	8	4	18	9	17	2	1	1	13	15	40040	3	15	2	240000	10	40044	86249	40044	86239	40044
240024	40043	299	0	0	0	0	0	0	0	115203	4826	0	26	275216	13	160000	13	160000	66	1599960	1	1	5	40024	0	40043	40043	9996	0	3	10022	160013	20	160000	20	480000	40043	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	4	19	15	17	2	2	2	15	16	40040	3	30	4	240000	10	40044	40044	40044	86249	40044
240024	40043	299	0	0	0	0	0	0	0	0	49	0	26	160013	13	276148	13	160000	68	11801742	1	1	5	40024	0	40043	40043	9996	0	3	56227	160013	20	160000	20	480000	85108	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	8	4	17	15	17	2	1	1	17	14	40040	3	15	2	240000	10	40044	40044	40044	40044	40044

TBX (two register table, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations