Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

TRN1 (vector, 2S)

Test 1: uops

Code:

  trn1 v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715001891687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646800201820372037157231895100010002000203720371110011000073116111817100020382038203820382038
100420371500611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  trn1 v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500600611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000126071011611197910100001002003820038200382003820038
1020420037155012001711968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500026219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000644141651019785010000102003820038200382003820038
1002420037150002621968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000164451651019785010000102003820038200382003820038
100242003715000262196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006441116111119785010000102003820038200382003820038
1002420037150015262196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006441016111119785010000102003820038200382003820038
100242003715000262196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006441016111019785010000102003820038200382003820038
100242003715009262196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006441016101119785010000102003820038200382003820038
100242003715000262196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006441116111019785010000102003820038200382003820038
100242003715000262196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006441016101119785010000102003820038200382003820038
100242003715000262196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006441016111019785010000102003820038200382003820038
100242003715000262196872510010101000010100006128476801200182003720037184443187671001020100002020000200372003711100211091010100001000006441016101019785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  trn1 v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003717300007508219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100001030710011611197910100001002003820038200382003820038
1020420037174000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000600150710011611197910100001002003820038200382003820038
10204200371740000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100002000710011611197910100001002003820038200382003820038
10204200371610000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100001000710011611197910100001002003820038200382003820038
10204200851610000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100002000710011611197910100001002003820038200382003820038
10204200371610000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000710011611197910100001002003820038200382003820038
102042003716100002106119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100002000710011611197910100001002003820038200382003820038
102042003716100001206119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100002060710011611197910100001002003820038200382003820038
1020420037155000090103196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000039030710011611197910100001002003820038200382003820038
10204200371560000120103196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000048060710011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371610000006119687251001010100002011368502847680120018200372003718444318767100102010000202000020037200371110021109101010000100496402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000426402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100196402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000006119687251002410100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000000015619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  trn1 v0.2s, v8.2s, v9.2s
  trn1 v1.2s, v8.2s, v9.2s
  trn1 v2.2s, v8.2s, v9.2s
  trn1 v3.2s, v8.2s, v9.2s
  trn1 v4.2s, v8.2s, v9.2s
  trn1 v5.2s, v8.2s, v9.2s
  trn1 v6.2s, v8.2s, v9.2s
  trn1 v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511031611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000000042025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000003000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000001030511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000030511011611200350800001002003920039200392003920039
8020420038150000000015025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000004000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815003925800101080000108000050640000102001920038200389996310018800102080000201600002003820038118002110910108000010030050200316532003580000102003920039200392003920039
8002420038150039258001010800001080000506400000720019200382003899963100188001020800002016000020038200381180021109101080000100386050200316352003580000102003920039200392003920039
800242003815003925800101080000108000050640000102001920038200389996310018800102080000201600002003820038118002110910108000010010050200516422003580000102003920039200392003920039
800242003815003925800101080000108000050640000072001920038200389996310018800102080000201600002003820038118002110910108000010000050200616652003580000102003920039200392003920039
800242003815003925800101080000108000050640000072001920038200389996310018800102080000201600002003820038118002110910108000010003050200516352003580000102003920039200392003920039
800242003814998125800101080000108000050640000072001920038200389996310018800102080000201600002003820038118002110910108000010000050200516562003580000102003920039200392003920039
800242003814903925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010013050200316352003580000102003920039201012003920039
800242003815003925800101080000108000050640000072001920038200879996310018800102080000201600002003820038118002110910108000010000050207316652003580000102003920039200392003920039
800242003815003925800101080000108000050640000072001920038200389996310018800102080000201600002003820038118002110910108000010000050207516332003580000102003920039200392003920039
800242003814903925800101080000108000050640000072001920038200389996310018800102080000201600002003820038118002110910108000010000050200316322003580000102003920039200392003920039