Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

TRN1 (vector, 8B)

Test 1: uops

Code:

  trn1 v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000173116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371605691687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715132611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371601401687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  trn1 v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100020857102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037149006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150018219687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001018220020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000006141968725100101010000101000050284768012001802003720037184443187671001022100002020000200372003711100211091010100001001006402162219785010000102003820038200382003820038
10024200371501100611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000006403162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001001626402162219785010000102003820038200382003820038
100242003715000002511968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000006403162219785010000102003820038200382003820038
100242003715000002561968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371490000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000006403162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000906403162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000006403162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  trn1 v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100990100100100001000710116111979102100001002003820038200382003820038
102042003715000003081968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100990100100100001000710116111979100100001002003820038200382003820038
10204200371490000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100990100100100001000710116311979100100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012012620037200831842231874510100200100002002000020037200371110201100990100100100001000710116111979100100001002003820038200382003820038
1020420037150000072619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009920021100100100001000710116111979100100001002003820038200382003820038
102042003715000132889211968725101001001000010010000500284768012001820037200371842231874510100206100002002000020037200371110201100990100100100001000710116111979100100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100990100100100001000710116111979100100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100990100100100001000710116411979110100001002003820038200382003820134
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002022000020037200371110201100990100100100001000710116111979100100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100990100100100001000710116111979100100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476801200182003720037184443187671001020101672020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150000004378196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500000061196672510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000000145196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000306622162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  trn1 v0.8b, v8.8b, v9.8b
  trn1 v1.8b, v8.8b, v9.8b
  trn1 v2.8b, v8.8b, v9.8b
  trn1 v3.8b, v8.8b, v9.8b
  trn1 v4.8b, v8.8b, v9.8b
  trn1 v5.8b, v8.8b, v9.8b
  trn1 v6.8b, v8.8b, v9.8b
  trn1 v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)l2 tlb miss data (0b)181e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)7bmap int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591560000000402580100100800001008000050064000012001920038200389973399968010002008000020016000020038200381180201100991001008000010000000511021611200350800001002003920039200392003920039
80204200381500000000402580100100800001008000050064000012001920038200389973399968010002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500000000402580100100800001008000050064000002001920038200389973399968010002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
802042003815000000001492580100100800001008000050064000012001920038200389973399968010002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
802042003815000000002112580100100800001008000050064000002001920038200389973399968010002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500000000402580100100800001008000050064000012001920038200389973399968010002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500000000402580100100800001008000050064000002001920038200389973399968010002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500000000402580100100800001008000050064000012001920038200389973399968010002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500000000402580100100800001008000050064000002001920038200389973399968010002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500000000402580100100800001008000050064000012001920038200389973399968010002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000010182580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502006165520035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502005165420035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502005165420035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502007168620035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502005165520035080000102003920039200392003920039
800242003815000036625800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020061666200351480000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502006165520035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502006165720035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502006167620035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502006166620035080000102003920039200392003920039