Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

TRN2 (vector, 8B)

Test 1: uops

Code:

  trn2 v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100002073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000373116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371606116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  trn2 v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000429611968725101001001000010010000500284768012001820037200371842203187451010020010000212200002003720037111020110099100100100001000037101161119791100001002003820038200382003820038
10204200371501000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119825100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842203187451058920010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000405611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000243611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371490000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000309611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000264611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500072611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000417611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010012101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000363611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  trn2 v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500001071968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000017101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715002401231968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500210611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500210611968725101001001000010010000500284768002001820037200371842203187451010020010000200203302008520037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037149000611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119847100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715515661968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006405166619785310000102003820038200382003820038
100242003715563141968725100101010000101000050284768002001820037200371844431876710010221000020200002003720037111002110910101000010000006407167719785010000102003820038200862003820038
100242003715034691968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006406166619785010000102003820038200382003820038
10024200371500611968725100101010000101015050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006407165719785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006407167719785010000102003820038200382003820038
100242003715004411968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006406167719785010000102003820038200382003820038
10024200371500711968725100101010000101000050284768002001820037200371844431876710010221000020200002003720037111002110910101000010000006407167719785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006405166519785010000102003820038200382003820038
1002420037150222611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006406166619785010000102003820038200382003820038
100242003715021611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006406166619785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  trn2 v0.8b, v8.8b, v9.8b
  trn2 v1.8b, v8.8b, v9.8b
  trn2 v2.8b, v8.8b, v9.8b
  trn2 v3.8b, v8.8b, v9.8b
  trn2 v4.8b, v8.8b, v9.8b
  trn2 v5.8b, v8.8b, v9.8b
  trn2 v6.8b, v8.8b, v9.8b
  trn2 v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420056150000001102580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000000511021611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000000511011611200350800001002003920039200392003920039
8020420038150000001452580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000000511011611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000000511011611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000010000511011611200350800001002003920039200392003920039
802042003815000000822580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000000511011611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000000511011611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000010000511011611200350800001002003920039200392003920039
8020420038154000006662580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000000511011611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715003024025800101080000108000050640000020019020038200389996310018800102080000201600002003820038118002110910108000010005024161615172003580000102003920039200392003920039
80024200381500024025800101080000108000050640000020019020038200389996310018800102080000201600002003820038118002110910108000010005024171618172003580000102003920039200392003920039
80024200381500024025800101080000108000050640000020019320038200389996310018800102080000201600002003820038118002110910108000010005024161617102003580000102003920039200392003920039
80024200381500024025800101080000108000050640000020019020038200389996310018800102080000201600002003820038118002110910108000010005024171620172003580000102003920039200392003920039
80024200381500024025800101080000108000050640000020019020038200389996310018800102080000201600002003820038118002110910108000010005024151617182003580000102003920039200392003920039
80024200381500024025800101080000108000050640000020019020038200389996310018800102080000201600002003820038118002110910108000010005024151618152003580000102003920039200392003920039
8002420038150028224025800101080000108000050640000020019020038200389996310018800102080000201600002003820038118002110910108000010005024171617162003580000102003920039200392003920039
80024200381500024025800101080000108000050640000020019020038200389996310018800102080000201600002003820038118002110910108000010005024181617172003580000102003920039200392003920039
80024200381500024025800101080000108000050640000020019020038200389996310018800102080000201600002003820038118002110910108000010005024171617172003580000102003920039200392003920039
8002420038150030270525800101080000108000050640000020019020038200389996310018800102080000201600002003820038118002110910108000010005024151616162003580000102003920039200392003920039