Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UABAL2 (vector, 4S)

Test 1: uops

Code:

  uabal2 v0.4s, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254825100010001000398313301830373037241532895100010003000303730371110011000000373116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
10043037230251254825100010001000398313301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
1004303723061254825100010001149398313301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010003000303730371110011000000373116112630100030383038303830383038
1004303722082254825100010001000398313301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
10043037232461254825100010001000398313301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  uabal2 v0.4s, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000380740031622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000360710021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000288266710021623296340100001003003830038300383003830038
10204300372250000019212954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000380710021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000370710021622296340100001003003830038300383003830038
10204300372250010061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000029710021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000393710021622296340100001003003830038300383003830038
102043003722500000726295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000063710021622296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000003710021622296340100001003003830038300383003830038
102043003722400000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000406710021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000001640216222963010000103003830038300383003830038
10024300372340061295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000030640216222963010000103003830038300833003830038
10024300372250061295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001020000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000000640316222963010000103003830038300383003830038
10024300372240061295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731330018300373003728287032876710010201000020300003003730037111002110910101000010000150640316222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000100640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  uabal2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722501452954825101001001000010010000500427731330018300373003728265032874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722502202954825101001001000010010000500427731330018300373003728265032874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731330018300373003728265032874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265032874510100200100002003000030037300371110202100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265032874510100200100002003000030037300371110201100991001001000010000007101161129634100001003008530086300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265032874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372240612954825101001001000710010000500427731330018300373003728265032874510100200100002003000030037300371110201100991001001000010003007101161129634100001003003830038300383003830038
102043003722501702954825101001001000010010000500427731330018300373003728265032874510100200100002003000030037300371110201100991001001000010001007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265032874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018300373003728265032874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000101606403163329630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
1002430037225000103295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038
1002430037225000726295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010006403163329630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  uabal2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000000088429548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710116111296340100001003003830038300383003830038
102043003722500000000063129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710116011296340100001003008530038300383003830038
10204300372240000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710116011296340100001003003830038300383003830038
10204300372250000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710116011296340100001003003830038300383003830038
10204300372250000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710116011296340100001003003830038300383003830038
10204300372250000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003721102011009910010010000100000000000710116011296340100001003003830038300383003830038
10204300372250000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710116011296340100001003003830038300383003830038
102043003722500000000072629548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710116011296340100001003003830038300383003830038
102043003722500000000072629548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710116011296340100001003003830038300383003830038
10204300372250000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710116011296340100001003003830038300383008630038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000306402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010447504277313130018300843008428287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830085
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300843003728287328767100102010000203000030037300371110021109101010000100010006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  uabal2 v0.4s, v8.8h, v9.8h
  movi v1.16b, 0
  uabal2 v1.4s, v8.8h, v9.8h
  movi v2.16b, 0
  uabal2 v2.4s, v8.8h, v9.8h
  movi v3.16b, 0
  uabal2 v3.4s, v8.8h, v9.8h
  movi v4.16b, 0
  uabal2 v4.4s, v8.8h, v9.8h
  movi v5.16b, 0
  uabal2 v5.4s, v8.8h, v9.8h
  movi v6.16b, 0
  uabal2 v6.4s, v8.8h, v9.8h
  movi v7.16b, 0
  uabal2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420089151039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111316112006101600001002006520065200652006520065
16020420064151039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010000010111116112006101600001002006520065200652006520065
16020420064151039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000100010111116112006101600001002006520065200652006520065
160204200641500148258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
16020420064151083258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520134200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020155200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
16020420064151039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200801500662780012128000012800006264000011020032200512005132280012208000020240000200642005111160021109101016000010000010028821425822143200482201160000102005220052200522005220052
160024200511500452780012128000012800006264000011520032200512005132280012208000020240000200852005111160021109101016000010000010026841521721155200482201160000102006120052200522005220052
160024200511500452780012128000012800006264000011520032200512005132280012208000020240000200852005111160021109101016000010000010026841522642244200572402160000102006120061200612006120061
1600242006015108827800121280000128000062640000015201512006020060322800122080000202400002008520060111600211091010160000100000100271151318322243200572402160000102005220061200612006120061
1600242006015005129800121280000128000062640000015200412006020060322800122080000202400002007320051111600211091010160000100300100301141322642237200482402160000102006120052200612006120061
1600242006015065129800121280000128000062640000115200412006020060322800122080000202400002006420060111600211091010160000100000100281142418942133200482402160000102006120052200612006120061
1600242006015005129800121280000128000062640000015200412006020060322800122080000202400002006420060111600211091010160000100000100311151417042144200482402160000102006120061200522006120061
160024200511510512980012128000012800006264000011520041200602005132280012208000020240000200852006011160021109101016000010000110028841317021144200482201160000102005220052200522005220052
160024200601500452780012128000012800006264000011520032200512005132280012208000020240000200642005111160021109101016000010000010027841416921153200482201160000102005220052200522005220052
160024200511500452780012128000012800006264000001520032200512005132280012208000020240000200852005111160021109101016000010000010028841520921144200482201160000102005220052200522005220052

Test 6: throughput

Count: 16

Code:

  uabal2 v0.4s, v16.8h, v17.8h
  uabal2 v1.4s, v16.8h, v17.8h
  uabal2 v2.4s, v16.8h, v17.8h
  uabal2 v3.4s, v16.8h, v17.8h
  uabal2 v4.4s, v16.8h, v17.8h
  uabal2 v5.4s, v16.8h, v17.8h
  uabal2 v6.4s, v16.8h, v17.8h
  uabal2 v7.4s, v16.8h, v17.8h
  uabal2 v8.4s, v16.8h, v17.8h
  uabal2 v9.4s, v16.8h, v17.8h
  uabal2 v10.4s, v16.8h, v17.8h
  uabal2 v11.4s, v16.8h, v17.8h
  uabal2 v12.4s, v16.8h, v17.8h
  uabal2 v13.4s, v16.8h, v17.8h
  uabal2 v14.4s, v16.8h, v17.8h
  uabal2 v15.4s, v16.8h, v17.8h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03091e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440059300001707025160117100160017100160000500239902714003040040400391997331999716010020016000020048000040051401271116020110099100100160000100010110216324003701600001004004040049400404004040049
1602044003930000051025160100100160000100160000500239899914003040040400391997331999716010020016000020048000040049400391116020110099100100160000100010110216334004501600001004004040050400404004040049
16020440039300001741025160117100160000100160000500128000014002040039400401997332000616010020016000020048000040039400491116020110099100100160000100010110216334004601600001004005040040400404004040040
16020440040299000410251601171001600171001600005001280000140020400484004019973319998160100200160000200480000400404004911160201100991001001600001001210110216334003601600001004004140049400404004940041
16020440048300001741025160100100160000100160000500128000014002040039400391997331999816010020016000020048000040040400391116020110099100100160000100010110316334003601600001004018940114401074010540049
160204400403001002540251602231001600011001600005001280000140020400494004919983132005116010020016000020048000040106400492116020110099100100160000100010151316334004501600001004004140040400414004940050
16020440040300001792025160117100160000100160000500243886514002140048400481997332000716010020016000020048000040039400481116020110099100100160000100010110316324004601600001004004040049400504004940049
16020440048300001741025160100100160018100160000500239899914002940049400491997331999816010020016000020048000040049400391116020110099100100160000100010110316324003701600001004004040049400414004940049
160204400493000011416025160100100160001100160000500128000014002940039400391997332000616010020016000020048000040049400481116020110099100100160000100010110316334003601600001004004040041400404004140050
1602044004830000150025160117100160000100160000500128000014002040040400391997331999716010020016000020048000040049400481116020110099100100160000100010110216324004601600001004004040040400414004040049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f373a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244005129910000000004602516001010160018101600005023989990104002040039400481998932001216001020160000204800004003940049111600211091010160000100000120000100246405316222234003604015160000104004040040400404004040050
16002440048299000000000052025160010101600171016000050128000001040029400394003919989320022160010201600002048000040039400391116002110910101600001000000000010024344741641234400460409160000104004040050400404004140049
1600244003930000000000007170251600271016001710160000501319998110400204003940039199893200121600102016000020480000400394003911160021109101016000010000000000100246397616422544003604015160000104004040040400494004040049
160024400393000000000000940251600271016001710160000501280000010400204003940048199893200121600102016000020480000400394004811160021109101016000010000000000100246423616422344004504015160000104004040040400414005040050
1600244003930000000000170610251600101016000010160000502399055010400304003940048199893200121600102016000020480000400484004011160022109101016000010000000000100243393516222554003604015160000104004940041400404004040048
160024400392990000000000520251600271016000010160000501280000010400204003940048199893200221600102016000020480000400394004811160021109101016000010000000000100243353516421544004602017160000104004040049400404004040050
1600244003930000000000170460251600101016000010160000502398999010400204004840040199893200221600102016000020480000400484003911160021109101016000010200000000100226403516412444004504015160000104004040049400414004140040
160024400483000000000000520251600271016000110160000501320000110400294003940039199893200221600102016000020480000400484003911160021109101016000010000000000100223397416222434004504015160000104005040040400404005040040
16002440039300000000000061025160011101600001016000050239899911040029400394003919989320022160010201600002048000040048400391116002110910101600001000000000010024336351642253400360408160000104004940040400494004140050
1600244004030000000000170460251600101016000010160000501280000010400204003940039199893200121600102016000020480000400394004811160021109101016000010000000000100246427416412574003604015160000104005040040400414004940040