Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UABAL (vector, 8H)

Test 1: uops

Code:

  uabal v0.8h, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723110165254825100010001000398313130183037303724153289510001000300030373037111001100000075516552630100030383038303830383038
1004303722110165254825100010001000398313130183037303724153289510001000300030373037111001100000075616762630100030383038303830383038
1004303722110165254825100010001000398313130183037303724153289510001000300030373037111001100000075616662630100030383038303830383038
1004303723110165254825100010001000398313130183037303724153289510001000300030373037111001100000075616552630100030383038303830383038
1004303722110165254825100010001000398313130183037303724153289510001000300030373037111001100000075516662630100030383038303830383038
1004303723110165254825100010001000398313130183037303724153289510001000300030373037111001100000077716662630100030383038303830383038
10043037231101107254825100010001000398313130183037303724153289510001000300030373037111001100010075616762630100030383038303830383038
1004303723110165254825100010001000398313130183037303724153289510001000300030373037111001100090075716662630100030383038303830383038
10043037231101107254825100010001000398313130183037303724153289510001000300030373037111001100000075616552630100030383038303830383038
1004303723110165254825100010001000398313130183037303724153289510001000300030373037111001100000075616662630100030383038303830383038

Test 2: Latency 1->1

Code:

  uabal v0.8h, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000712954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710121622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710121622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710121622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000600710121622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710121622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710121622296340100001003003830038300383003830038
1020430037225000000010082954825101001001000010010000500427731303001830037300372826532874510100200101802003000030037300371110201100991001001000010000010000710121622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710121622296340100001003003830038300383003830038
10204300372240000000612954825101001001000810010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710121622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710131622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243008422405812954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722509952954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103037030038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037211002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372253612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372259612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  uabal v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250006129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000007102161129634100001003003830038300383003830038
10204300372240006129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722400025129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722500044129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100003007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100010007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000640316222963010000103003830038300383003830038
1002430037225084295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000640316222963010000103003830038300383003830038
1002430037224061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000030640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000001640316222963010000103003830038300383003830038
10024300372241561295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000640316222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  uabal v0.8h, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071011611296340100001003003830038300383003830038
102043003722500000001032954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000030071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071011611296340100001003003830038300383003830038
10204300372240000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731330018300373003728287328767100102010000203048630037300371110021109101010000102300640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250842954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  uabal v0.8h, v8.8b, v9.8b
  movi v1.16b, 0
  uabal v1.8h, v8.8b, v9.8b
  movi v2.16b, 0
  uabal v2.8h, v8.8b, v9.8b
  movi v3.16b, 0
  uabal v3.8h, v8.8b, v9.8b
  movi v4.16b, 0
  uabal v4.8h, v8.8b, v9.8b
  movi v5.16b, 0
  uabal v5.8h, v8.8b, v9.8b
  movi v6.16b, 0
  uabal v6.8h, v8.8b, v9.8b
  movi v7.16b, 0
  uabal v7.8h, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008815000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111116112006101600001002006520065200652006520065
1602042006415000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111116112006101600001002006520065200652006520065
1602042006415000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111116112006101600001002006520065200652006520065
1602042006415000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111116112006101600001002006520065200652006520065
16020420064151000104258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111116112006101600001002006520065200652006520065
1602042006415000060258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111116112006101600001002006520065200652006520065
16020420064150000229258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111116112006101600001002006520065200652006520065
1602042006415000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111116112006101600001002006520065200652006520065
1602042006415000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111116112006101600001002006520065200652006520065
16020420064151000104258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111116112006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6erob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200861500019327800121280000128000062640000115200322005120051032280012208000020240000200602006011160021109101016000010000010041841103422168200482402160000102006120061200612006120061
1600242005115000452780012128000012800006264000001520032200512005103228001220800002024000020051200511116002110910101600001000001003383152521164200482201160000102006120052200522005220052
1600242005115000452780012128000012800006264000011520032200512005103228001220800002024000020051200511116002110910101600001000001003183142521166200482201160000102005220052200522005220052
1600242005115000512780012128000012800006264000011520032200512005103228001220800002024000020051200511116002110910101600001000001003283172521143200482201160000102005220052200522005220052
1600242005115000452780012128000012800006264000011520032200512005103228001220800002024000020051200511116002110910101600001000001003083162521134200482201160000102005220052200522005220052
1600242005115100872780012128000012800006264000011520032200512005103228001220800002024000020051200511116002110910101600001000001003383152521134200482201160000102005220052200522005220052
16002420051150002352780012128000012800006264000011520032200512005103228001220800002024000020051200511116002110910101600001000001003783152521174200482201160000102005220052200522005220052
1600242005115000452780012128000012800006264000011520032200512005103228001220800002024000020051200511116002110910101600001000001003883152521166200482201160000102005220052200522005220052
16002420051150001332780012128000012800006264000011520032200512005103228001220800002024000020051200511116002110910101600001000001004383162541134200482201160000102005220052200522005220052
1600242005115000452780012128000012800006264000011520032200512005103228001220800002024000020051200511116002110910101600001000001003383152521143200482231160000102005220052200522005220052

Test 6: throughput

Count: 16

Code:

  uabal v0.8h, v16.8b, v17.8b
  uabal v1.8h, v16.8b, v17.8b
  uabal v2.8h, v16.8b, v17.8b
  uabal v3.8h, v16.8b, v17.8b
  uabal v4.8h, v16.8b, v17.8b
  uabal v5.8h, v16.8b, v17.8b
  uabal v6.8h, v16.8b, v17.8b
  uabal v7.8h, v16.8b, v17.8b
  uabal v8.8h, v16.8b, v17.8b
  uabal v9.8h, v16.8b, v17.8b
  uabal v10.8h, v16.8b, v17.8b
  uabal v11.8h, v16.8b, v17.8b
  uabal v12.8h, v16.8b, v17.8b
  uabal v13.8h, v16.8b, v17.8b
  uabal v14.8h, v16.8b, v17.8b
  uabal v15.8h, v16.8b, v17.8b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)0309l2 tlb miss data (0b)181e1f373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044005230000000184125160100100160018116160000500286976304006904004940116200257200071601002001601632004800004003940039311602011009910010016000010006634010110216114003601600001004004040050400404004040040
1602044003930000000041251601001001600171001600005001280000140030040039400391997331999716010020016000020048000040039400391116020110099100100160000100030010110116114003601600001004005040050400504005040040
1602044003929900000041251601171001600001001600005001280000040020040039400391997332000616010020016000020048000040039400391116020110099100100160000100030010110116114003601600001004020940199405094016440197
160204401993011112701783251601181001600001001600005001280000040021040039400391997331999716010020016000020048000040048400521116020110099100100160000100000010110116114003601600001004004040040400404004040040
1602044008929900000041251601181001600181001600005002438865040030040039400491997331999716010020016000020048000040049400401116020110099100100160000100000010110116114004601600001004004940040400504005040040
1602044003929900000041251601001001600001001600005001819318040020040039400391997331999716010020016000020048000040039400391116020110099100100160000100000010110116114003601600001004004040040400404004040040
1602044003929900000041251601001001600001001600005001280000040020040039400391997331999716010020016000020048000040040400391116020110099100100160000100000010110116114003601600001004004040050400404004040040
1602044003930000000041251601001001600181001600005002438865040021040039400401997332000616010020016000020048000040039400391116020110099100100160000100000010110116114003601600001004004040040400404004040040
1602044003929900000041251601171001600001001600005001280000040020040039400391997331999716010020016000020048000040049400491116020110099100100160000100000010110116114003601600001004004040040400404004040040
1602044003930000000046251601181001600181001600005001280000040020040039400391997331999716010020016000020048000040039400391116020110099100100160000100000010110116114003601600001004004040049400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f373a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400493000000000000046025160010101600001216000050128000001400200400394004919996032002016001020160000204800004003940039111600211091010160000100000300100246221316422554003603010160000104004040040400404005040040
1600244004930000000000000460251600101016000010160000501280000114002004003940039199960320019160010201600002048000040049400391116002110910101600001000000001002231151621154400360155160000104004040050400404004040040
16002440039299000000000005202516001010160000101600005012800000140030040049400491999603200541600102016000020480000400484004811160021109101016000010000000010024622516422454003603010160000104004040040400404005040040
16002440039300000000000006202516001010160000101600005012800000140020040039400391999603200281600102016000020480000400394003911160021109101016000010000000010024622416422454003603010160000104004140049400404005040049
1600244004030000000000000520251600101016000010160000502398999014002104003940040199960320029160010201600002048000040049400491116002110910101600001000000001002262241621155400360155160000104004040040400404004040040
16002440039300000000000005602516001010160000101600005024388651140029040039400391999603200281600102016000020480000400394003911160021109101016000010000200010022321516212554003601510160000104005040040400414004040040
16002440039300000000000004602516002710160018101600005012800001140020040039400391999603200191600102016000020480000400484004811160021109101016000010000000010022312417222544003601510160000104004040040400404004040040
1600244003930000000000000550251600101016000010160000502398999114002004003940039199960320019160010201600002048000040039400391116002110910101600001000000001002262151622255400360155160000104004940049400494004040040
16002440039300000000000005202516001010160000101600005012800000040020040039400391999603200191600102016000020480000400394004011160021109101016000010000000010024321516211554004501510160000104004040040400404004140040
1600244004930000000000000460251600101016000110160000501280000104002004003940039199960320019160010201600002048000040039400391116002110910101600001000000001002231151621245400460155160000104005040050400404004040050