Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UABA (vector, 2S)

Test 1: uops

Code:

  uaba v0.2s, v1.2s, v2.2s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723006125482510001000100039831313018303730372415328951000100030003037303711100110000073216222630100030383038303830383038
1004303722008425482510001000100039831313018303730372415328951000100030003037303711100110000073216222630100030383038303830383038
1004303722006125482510001000100039831303018303730372415328951000100030003037303711100110000073216222630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100030003037303711100110000373216222630100030383038303830383038
100430372300147254825100010001000398313030183037303724153289510001000300030373037111001100001273216222630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100030003037303711100110000073216222630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100030003037303711100110000073216222630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100030003037303711100110000073216222630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100030003037303711100110000073216222630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100030003037303711100110000073216222630100030383038303830383038

Test 2: Latency 1->1

Code:

  uaba v0.2s, v1.2s, v2.2s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225100100000165295482510100100100001001000050042773131300183003730037282726287401010020010008200300243003730037111020110099100100100001000000000111721031633296470100001003003830038300383003830038
10204300372251001000001216295482510100100100001001000050042773131300183003730037282726287411010020010008200300243003730037111020110099100100100001000000030111724031633296460100001003003830038300383003830038
1020430037225100100000165295482510100100100001001000050042773131300183003730037282726287401010020010008200300243003730037211020110099100100100001000000030111721031631296460100001003003830038300383003830038
1020430037225100100000165295482510100100100001001000050042773131300183003730037282727287411010020010008200300243003730037111020110099100100100001000200000111721031631296470100001003003830038300383003830038
1020430037225100100000165295482510100100100001001000050042773131300183003730037282726287411010020010008200300243003730037111020110099100100100001000000000111720031613296460100001003003830038300383003830038
1020430037224100100000165295482510100100100001001000050042773131300183003730037282727287401010020010008200300243003730037111020110099100100100001000000000111720041633296470100001003003830038300383003830038
1020430037225100100000165295482510100100100001001000050042773131300183003730037282726287411010020010008200300243003730037111020110099100100100001000000000111720011633296470100001003003830038300383003830038
1020430037224100100000165295482510100100100001001000050042773131300183003730037282726287411010020010008200300243003730037111020110099100100100001000000000111720031631296470100001003003830085300383003830038
10204300372251001000001862954825101001001000010010000500427731313001830131300372827262874110100200100082003053730086300371110201100991001001000010014001000111720032413296460100001003003830038300383003830038
1020430037225100100000165295482510100100100001001000050042773131300183003730037282726287411010020010008200300243003730037111020110099100100100001000000030111721031631296470100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
1002430037225000000042229548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000003640216222963010000103003830038300383003830038
100243003722401000006129548251001010100001010000504277313130018300373003728299328767100102010000203000030037300371110021109101010000100000100640294322963010000103003830038300383003830038
100243003722400000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000102000000640216222963010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640416322963010000103003830038300383003830038
1002430037225000039006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000100640216422963010000103003830038300383003830038
1002430037224000000010329548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000100640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  uaba v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037302291110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010020000071011611296340100001003003830038300383003830038
1020430084225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000658427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
10204300372250018612954825101001001000010010000500427731313001830037300372826532876310100200100002003000030037300371110201100991001001000010002000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037233000012001732954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037232000012005692954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000002542954825100101010000101014950427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000002532954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010020000006402162229630010000103003830038300383003830038
100243003722400000002522954825100101010000101000050427731303001830037300372830732876710010201000020300003003730037111002110910101000010000400006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  uaba v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000570082295482510100100100001001000050042773131300183003730037282653287451010020010000200305013008530037111020110099100100100001000000102836071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000001200103295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
102043003722400000120061295482510100100100001001000062642773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037224000001200612954825101001001000010010000500427731303001830037300372826532876310100200100002003000030037300371110201100991001001000010000000022780710116112963425100001003008730038300383003830038
102043003722510100000103295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000103071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000003071011611296340100001003003830038300383003830038
102043003722500000120061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287025287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373022811100211091010100001000002640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100171010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373018011100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640316222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  uaba v0.2s, v8.2s, v9.2s
  movi v1.16b, 0
  uaba v1.2s, v8.2s, v9.2s
  movi v2.16b, 0
  uaba v2.2s, v8.2s, v9.2s
  movi v3.16b, 0
  uaba v3.2s, v8.2s, v9.2s
  movi v4.16b, 0
  uaba v4.2s, v8.2s, v9.2s
  movi v5.16b, 0
  uaba v5.2s, v8.2s, v9.2s
  movi v6.16b, 0
  uaba v6.2s, v8.2s, v9.2s
  movi v7.16b, 0
  uaba v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200891500392580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001001011121611200611600001002006520065200652006520065
1602042006415109532580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001001011111611200611600001002006520065200652006520065
160204200641500392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001001011111611200611600001002006520065200652006520065
160204200641510392580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001001011111611200611600001002006520065200652006520065
160204200641500392580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001001011111611200611600001002006520065200652006520065
160204200641510602580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001001011111611200611600001002006520065200652006520065
1602042006415008202580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001001011111611200611600001002006520065200652006520065
160204200641500392580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001001011111611200611600001002006520065200652006520065
1602042006415009182580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001001011111611200611600001002006520065200652006520065
160204200642980392580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001001011111611200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200521500000452580012128000012800006264000011200272004620046322800122080000202400002004620289111600211091010160000100001002873119202117720043215160000102004720047200472004720047
160024200461500000892580012128000012800006264000011200272004620046322800122080000202400002004620046111600211091010160000100001002864115202115720043215160000102004720047200472004720047
160024200461520000452580012128000012800006264000011200272004620046322800122080000202400002004620046111600211091010160000100001006070213244125320047230160000102005120047200512005120051
160024200501510000512580012128000012800006264000001200312005020050322800122080000202400002005020050111600211091010160000100001002964225204223520047230160000102005120051200512005120051
160024200501500000512580012128000012800006264000001200312005020050322800122080000202400002005020050111600211091010160000100001003170223244226320047230160000102005120051200512005120051
160024200501500000512580012128000012800006264000001200312005020050322800122080000202400002005020046111600211091010160000100001003164223244223520047230160000102005120051200512005120051
160024200501500000452580012128000012800006264000001200312005020050322800122080000202400002005020050111600211091010160000100001003161225244225520047230160000102005120051200512005120047
160024200501500000512580012128000012800006264000001200312005020050322800122080000202400002005020050111600211091010160000100001002967225244225320047230160000102005120051200512005120051
160024200501510000512580012128000012800006264000001200312005020050322800122080000202400002005020050111600211091010160000100001003161225244225320047230160000102005120051200512005120051
160024200501500000512580012128000012800006264000001200312005020050322800122080000202400002005020050111600211091010160000106001002967225244223520047230160000102005120051200512005120051

Test 6: throughput

Count: 16

Code:

  uaba v0.2s, v16.2s, v17.2s
  uaba v1.2s, v16.2s, v17.2s
  uaba v2.2s, v16.2s, v17.2s
  uaba v3.2s, v16.2s, v17.2s
  uaba v4.2s, v16.2s, v17.2s
  uaba v5.2s, v16.2s, v17.2s
  uaba v6.2s, v16.2s, v17.2s
  uaba v7.2s, v16.2s, v17.2s
  uaba v8.2s, v16.2s, v17.2s
  uaba v9.2s, v16.2s, v17.2s
  uaba v10.2s, v16.2s, v17.2s
  uaba v11.2s, v16.2s, v17.2s
  uaba v12.2s, v16.2s, v17.2s
  uaba v13.2s, v16.2s, v17.2s
  uaba v14.2s, v16.2s, v17.2s
  uaba v15.2s, v16.2s, v17.2s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440060300000000000172230251601171001600091001600205002399187140030400484003919977619991160120200160032200480096400394004911160201100991001001600001000000011110123116004004501600001004004040049400404005040041
160204400393000000000000390251601081001600081001600205001280132140021400394004919977619999160120200160032202480096400394010611160201100991001001600001000000011110118016004004601600001004004040040400504005040041
16020440039300000000000174100251601171001600171001600205002399131140029400394003919977619999160120200160032200480096400494004911160201100991001001600001000000011110118016004004601600001004004940072400404004940072
1602044004830000000000017300251601171001600081001600205002399131040020400394004819977619990160120200160032200480096400484007111160201100991001001600001000000011110118016004003601600001004004040040400404004040049
160204400402990000000000390251601081001600001001600005001280000040029400394004919973320007160100200160000200480000400494003911160201100991001001600001000000000010110116114003601600001004007240040400404005040040
1602044004929900000000017410251601171001600611001600005002398999040029400394004819973319997160100200160000200480000400394003911160201100991001001600001000000000010110116114004501600001004004140040400494004940040
1602044003930000000000017510251601001001600001001600005002398999140030400484003919973319997160100200160463200480000400484004811160201100991001001600001000000000010110116114004601600001004004940072400404004040049
1602044003930000000000017410251601001001600001001600005001280000140029400714003919973319997160100200160000200480000400394004811160201100991001001600001000000000010110116114003701600001004004040040400414004040049
160204400393000000000000420251601001001600001001600005001280000040029400494003919973320006160100200160000200480000400494003911160201100991001001600001000003000010110116114003601600001004007240040400404004140040
1602044004930000000000017410251601171001600171001600005001280000140020400394003919973320006160100200160000200480000400394003911160201100991001001600001000000000010110116114003601600001004005040049400404005040050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03l1i tlb fill (04)l2 tlb miss instruction (0a)1e373a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440049300200170562516002710160017101600005013199971140020400394003919996320020160010201600002048000040048400481116002110910101600001000010106311032162112329400360209160000104004940049400404004040049
160024400483000001707525160011101600011016000050131999701400214003940048199963200281600102016000020480000400394004811160021109101016000010000100986421231632229234004504113160000104004940049400494004940050
160024400483001103417525160011101600171016000050239899901400204004840048199963200201600102016000020480000400404010811160021109101016000010000100926421291632219294004504114160000104004940040400404004940049
160024400482991001708425160027101600171016000050131999701400294004840040199963200191600102016000020480000400404004811160021109101016000010000100926421281632219294004504118160000104004940049400494004940049
160024400483001001709025160027101600171016000050239899901400304004840048199963200281600102016000020480000400484004811160021109101016000010000100896421281632229314004504113160000104004940049400494004940049
16002440040299100170124225160011101600011016000050131999701400294004840040199963200201601232016000020480000400484004811160021109101016000010000100926421301632231184003604115160000104004140049400414004040041
160024400403001001707625160027101600171016000050239899901400294004840048199963200281600102016000020480000400484004811160021109101016000010000100906421281632228294003604118160000104004940049400494004940049
160024400393001001709025160011101600011016000050239899901400204004840048199963200281600102016046920480000400484010711160021109101016000010000100716421311632230304004504115160000104004140049400414004040049
160024400483001001708425160027101600171016000050239899901400214004040040199963200281600102016000020480000400484004811160021109101016000010000100906421181632230184004504118160000104004940040400494004040040
16002440048300100119025160011101600171016000050128000001400214003940048199963200191600102016000020480000400484004811160021109101016000010000100916421311632233194003704115160000104004140040400494004140049