Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
uaba v0.2s, v1.2s, v2.2s
movi v0.16b, 1 movi v1.16b, 2 movi v2.16b, 3
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | 18 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd alu (9a) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
1004 | 3037 | 23 | 0 | 0 | 61 | 2548 | 25 | 1000 | 1000 | 1000 | 398313 | 1 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 3000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 2630 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 22 | 0 | 0 | 84 | 2548 | 25 | 1000 | 1000 | 1000 | 398313 | 1 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 3000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 2630 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 22 | 0 | 0 | 61 | 2548 | 25 | 1000 | 1000 | 1000 | 398313 | 0 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 3000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 2630 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 0 | 61 | 2548 | 25 | 1000 | 1000 | 1000 | 398313 | 0 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 3000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 3 | 73 | 2 | 16 | 2 | 2 | 2630 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 0 | 147 | 2548 | 25 | 1000 | 1000 | 1000 | 398313 | 0 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 3000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 12 | 73 | 2 | 16 | 2 | 2 | 2630 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 0 | 61 | 2548 | 25 | 1000 | 1000 | 1000 | 398313 | 0 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 3000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 2630 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 22 | 0 | 0 | 61 | 2548 | 25 | 1000 | 1000 | 1000 | 398313 | 1 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 3000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 2630 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 0 | 61 | 2548 | 25 | 1000 | 1000 | 1000 | 398313 | 0 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 3000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 2630 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 22 | 0 | 0 | 61 | 2548 | 25 | 1000 | 1000 | 1000 | 398313 | 1 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 3000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 2630 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 0 | 61 | 2548 | 25 | 1000 | 1000 | 1000 | 398313 | 1 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 3000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 2630 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
Code:
uaba v0.2s, v1.2s, v2.2s
movi v0.16b, 1 movi v1.16b, 2 movi v2.16b, 3
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0037
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3a | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 30037 | 225 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 65 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28272 | 6 | 28740 | 10100 | 200 | 10008 | 200 | 30024 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 721 | 0 | 3 | 16 | 3 | 3 | 29647 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 216 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28272 | 6 | 28741 | 10100 | 200 | 10008 | 200 | 30024 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 1 | 1 | 1 | 724 | 0 | 3 | 16 | 3 | 3 | 29646 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 65 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28272 | 6 | 28740 | 10100 | 200 | 10008 | 200 | 30024 | 30037 | 30037 | 2 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 1 | 1 | 1 | 721 | 0 | 3 | 16 | 3 | 1 | 29646 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 65 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28272 | 7 | 28741 | 10100 | 200 | 10008 | 200 | 30024 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 721 | 0 | 3 | 16 | 3 | 1 | 29647 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 65 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28272 | 6 | 28741 | 10100 | 200 | 10008 | 200 | 30024 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 720 | 0 | 3 | 16 | 1 | 3 | 29646 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 224 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 65 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28272 | 7 | 28740 | 10100 | 200 | 10008 | 200 | 30024 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 720 | 0 | 4 | 16 | 3 | 3 | 29647 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 65 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28272 | 6 | 28741 | 10100 | 200 | 10008 | 200 | 30024 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 720 | 0 | 1 | 16 | 3 | 3 | 29647 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 224 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 65 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28272 | 6 | 28741 | 10100 | 200 | 10008 | 200 | 30024 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 720 | 0 | 3 | 16 | 3 | 1 | 29647 | 0 | 10000 | 100 | 30038 | 30085 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 86 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30131 | 30037 | 28272 | 6 | 28741 | 10100 | 200 | 10008 | 200 | 30537 | 30086 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 720 | 0 | 3 | 24 | 1 | 3 | 29646 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 65 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28272 | 6 | 28741 | 10100 | 200 | 10008 | 200 | 30024 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 1 | 1 | 1 | 721 | 0 | 3 | 16 | 3 | 1 | 29647 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
Result (median cycles for code): 3.0037
retire uop (01) | cycle (02) | 03 | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3a | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 422 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 0 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 224 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28299 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 640 | 2 | 94 | 3 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 224 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 4 | 16 | 3 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 39 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 640 | 2 | 16 | 4 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 224 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 103 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
Code:
uaba v0.2s, v0.2s, v1.2s
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0037
retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 18 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache writeback (a8) | a9 | ac | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30229 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 2 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30084 | 225 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 658 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 18 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28763 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 2 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
Result (median cycles for code): 3.0037
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 18 | 19 | 1e | 1f | 3a | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 30037 | 233 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 173 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 232 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 569 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 254 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10149 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 253 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 0 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 224 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 252 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 0 | 30018 | 30037 | 30037 | 28307 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
Code:
uaba v0.2s, v1.2s, v0.2s
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0037
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | 18 | 19 | 1e | 1f | 3a | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 57 | 0 | 0 | 82 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 1 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30501 | 30085 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 1 | 0 | 2836 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 0 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 0 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 103 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 0 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 224 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 626 | 4277313 | 0 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 224 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 0 | 30018 | 30037 | 30037 | 28265 | 3 | 28763 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 2278 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 25 | 10000 | 100 | 30087 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 103 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 0 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 1 | 0 | 3 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 0 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 0 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 61 | 29548 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277313 | 0 | 30018 | 30037 | 30037 | 28265 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 30000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29634 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
Result (median cycles for code): 3.0037
retire uop (01) | cycle (02) | 03 | 1e | 1f | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | ld unit uop (a6) | l1d cache writeback (a8) | ac | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 30037 | 225 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 0 | 25 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30228 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 2 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 61 | 29548 | 25 | 10017 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30180 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 61 | 29548 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277313 | 1 | 30018 | 30037 | 30037 | 28287 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 30000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 2 | 2 | 29630 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
Count: 8
Code:
movi v0.16b, 0 uaba v0.2s, v8.2s, v9.2s movi v1.16b, 0 uaba v1.2s, v8.2s, v9.2s movi v2.16b, 0 uaba v2.2s, v8.2s, v9.2s movi v3.16b, 0 uaba v3.2s, v8.2s, v9.2s movi v4.16b, 0 uaba v4.2s, v8.2s, v9.2s movi v5.16b, 0 uaba v5.2s, v8.2s, v9.2s movi v6.16b, 0 uaba v6.2s, v8.2s, v9.2s movi v7.16b, 0 uaba v7.2s, v8.2s, v9.2s
movi v8.16b, 9 movi v9.16b, 10
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2508
retire uop (01) | cycle (02) | 03 | 1f | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160204 | 20089 | 150 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20045 | 20064 | 20064 | 3 | 22 | 80100 | 200 | 80000 | 200 | 240000 | 20064 | 20064 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 10111 | 2 | 16 | 1 | 1 | 20061 | 160000 | 100 | 20065 | 20065 | 20065 | 20065 | 20065 |
160204 | 20064 | 151 | 0 | 953 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20045 | 20064 | 20064 | 3 | 22 | 80100 | 200 | 80000 | 200 | 240000 | 20064 | 20064 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 10111 | 1 | 16 | 1 | 1 | 20061 | 160000 | 100 | 20065 | 20065 | 20065 | 20065 | 20065 |
160204 | 20064 | 150 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 1 | 20045 | 20064 | 20064 | 3 | 22 | 80100 | 200 | 80000 | 200 | 240000 | 20064 | 20064 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 10111 | 1 | 16 | 1 | 1 | 20061 | 160000 | 100 | 20065 | 20065 | 20065 | 20065 | 20065 |
160204 | 20064 | 151 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20045 | 20064 | 20064 | 3 | 22 | 80100 | 200 | 80000 | 200 | 240000 | 20064 | 20064 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 10111 | 1 | 16 | 1 | 1 | 20061 | 160000 | 100 | 20065 | 20065 | 20065 | 20065 | 20065 |
160204 | 20064 | 150 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20045 | 20064 | 20064 | 3 | 22 | 80100 | 200 | 80000 | 200 | 240000 | 20064 | 20064 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 10111 | 1 | 16 | 1 | 1 | 20061 | 160000 | 100 | 20065 | 20065 | 20065 | 20065 | 20065 |
160204 | 20064 | 151 | 0 | 60 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20045 | 20064 | 20064 | 3 | 22 | 80100 | 200 | 80000 | 200 | 240000 | 20064 | 20064 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 10111 | 1 | 16 | 1 | 1 | 20061 | 160000 | 100 | 20065 | 20065 | 20065 | 20065 | 20065 |
160204 | 20064 | 150 | 0 | 820 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20045 | 20064 | 20064 | 3 | 22 | 80100 | 200 | 80000 | 200 | 240000 | 20064 | 20064 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 10111 | 1 | 16 | 1 | 1 | 20061 | 160000 | 100 | 20065 | 20065 | 20065 | 20065 | 20065 |
160204 | 20064 | 150 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20045 | 20064 | 20064 | 3 | 22 | 80100 | 200 | 80000 | 200 | 240000 | 20064 | 20064 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 10111 | 1 | 16 | 1 | 1 | 20061 | 160000 | 100 | 20065 | 20065 | 20065 | 20065 | 20065 |
160204 | 20064 | 150 | 0 | 918 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20045 | 20064 | 20064 | 3 | 22 | 80100 | 200 | 80000 | 200 | 240000 | 20064 | 20064 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 10111 | 1 | 16 | 1 | 1 | 20061 | 160000 | 100 | 20065 | 20065 | 20065 | 20065 | 20065 |
160204 | 20064 | 298 | 0 | 39 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20045 | 20064 | 20064 | 3 | 22 | 80100 | 200 | 80000 | 200 | 240000 | 20064 | 20064 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 10111 | 1 | 16 | 1 | 1 | 20061 | 160000 | 100 | 20065 | 20065 | 20065 | 20065 | 20065 |
Result (median cycles for code divided by count): 0.2506
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 18 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 5f | 60 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160024 | 20052 | 150 | 0 | 0 | 0 | 0 | 45 | 25 | 80012 | 12 | 80000 | 12 | 80000 | 62 | 640000 | 1 | 1 | 20027 | 20046 | 20046 | 3 | 22 | 80012 | 20 | 80000 | 20 | 240000 | 20046 | 20289 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10028 | 73 | 1 | 1 | 9 | 20 | 2 | 1 | 1 | 7 | 7 | 20043 | 2 | 15 | 160000 | 10 | 20047 | 20047 | 20047 | 20047 | 20047 |
160024 | 20046 | 150 | 0 | 0 | 0 | 0 | 89 | 25 | 80012 | 12 | 80000 | 12 | 80000 | 62 | 640000 | 1 | 1 | 20027 | 20046 | 20046 | 3 | 22 | 80012 | 20 | 80000 | 20 | 240000 | 20046 | 20046 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10028 | 64 | 1 | 1 | 5 | 20 | 2 | 1 | 1 | 5 | 7 | 20043 | 2 | 15 | 160000 | 10 | 20047 | 20047 | 20047 | 20047 | 20047 |
160024 | 20046 | 152 | 0 | 0 | 0 | 0 | 45 | 25 | 80012 | 12 | 80000 | 12 | 80000 | 62 | 640000 | 1 | 1 | 20027 | 20046 | 20046 | 3 | 22 | 80012 | 20 | 80000 | 20 | 240000 | 20046 | 20046 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10060 | 70 | 2 | 1 | 3 | 24 | 4 | 1 | 2 | 5 | 3 | 20047 | 2 | 30 | 160000 | 10 | 20051 | 20047 | 20051 | 20051 | 20051 |
160024 | 20050 | 151 | 0 | 0 | 0 | 0 | 51 | 25 | 80012 | 12 | 80000 | 12 | 80000 | 62 | 640000 | 0 | 1 | 20031 | 20050 | 20050 | 3 | 22 | 80012 | 20 | 80000 | 20 | 240000 | 20050 | 20050 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10029 | 64 | 2 | 2 | 5 | 20 | 4 | 2 | 2 | 3 | 5 | 20047 | 2 | 30 | 160000 | 10 | 20051 | 20051 | 20051 | 20051 | 20051 |
160024 | 20050 | 150 | 0 | 0 | 0 | 0 | 51 | 25 | 80012 | 12 | 80000 | 12 | 80000 | 62 | 640000 | 0 | 1 | 20031 | 20050 | 20050 | 3 | 22 | 80012 | 20 | 80000 | 20 | 240000 | 20050 | 20050 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10031 | 70 | 2 | 2 | 3 | 24 | 4 | 2 | 2 | 6 | 3 | 20047 | 2 | 30 | 160000 | 10 | 20051 | 20051 | 20051 | 20051 | 20051 |
160024 | 20050 | 150 | 0 | 0 | 0 | 0 | 51 | 25 | 80012 | 12 | 80000 | 12 | 80000 | 62 | 640000 | 0 | 1 | 20031 | 20050 | 20050 | 3 | 22 | 80012 | 20 | 80000 | 20 | 240000 | 20050 | 20046 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10031 | 64 | 2 | 2 | 3 | 24 | 4 | 2 | 2 | 3 | 5 | 20047 | 2 | 30 | 160000 | 10 | 20051 | 20051 | 20051 | 20051 | 20051 |
160024 | 20050 | 150 | 0 | 0 | 0 | 0 | 45 | 25 | 80012 | 12 | 80000 | 12 | 80000 | 62 | 640000 | 0 | 1 | 20031 | 20050 | 20050 | 3 | 22 | 80012 | 20 | 80000 | 20 | 240000 | 20050 | 20050 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10031 | 61 | 2 | 2 | 5 | 24 | 4 | 2 | 2 | 5 | 5 | 20047 | 2 | 30 | 160000 | 10 | 20051 | 20051 | 20051 | 20051 | 20047 |
160024 | 20050 | 150 | 0 | 0 | 0 | 0 | 51 | 25 | 80012 | 12 | 80000 | 12 | 80000 | 62 | 640000 | 0 | 1 | 20031 | 20050 | 20050 | 3 | 22 | 80012 | 20 | 80000 | 20 | 240000 | 20050 | 20050 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10029 | 67 | 2 | 2 | 5 | 24 | 4 | 2 | 2 | 5 | 3 | 20047 | 2 | 30 | 160000 | 10 | 20051 | 20051 | 20051 | 20051 | 20051 |
160024 | 20050 | 151 | 0 | 0 | 0 | 0 | 51 | 25 | 80012 | 12 | 80000 | 12 | 80000 | 62 | 640000 | 0 | 1 | 20031 | 20050 | 20050 | 3 | 22 | 80012 | 20 | 80000 | 20 | 240000 | 20050 | 20050 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10031 | 61 | 2 | 2 | 5 | 24 | 4 | 2 | 2 | 5 | 3 | 20047 | 2 | 30 | 160000 | 10 | 20051 | 20051 | 20051 | 20051 | 20051 |
160024 | 20050 | 150 | 0 | 0 | 0 | 0 | 51 | 25 | 80012 | 12 | 80000 | 12 | 80000 | 62 | 640000 | 0 | 1 | 20031 | 20050 | 20050 | 3 | 22 | 80012 | 20 | 80000 | 20 | 240000 | 20050 | 20050 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 6 | 0 | 0 | 10029 | 67 | 2 | 2 | 5 | 24 | 4 | 2 | 2 | 3 | 5 | 20047 | 2 | 30 | 160000 | 10 | 20051 | 20051 | 20051 | 20051 | 20051 |
Count: 16
Code:
uaba v0.2s, v16.2s, v17.2s uaba v1.2s, v16.2s, v17.2s uaba v2.2s, v16.2s, v17.2s uaba v3.2s, v16.2s, v17.2s uaba v4.2s, v16.2s, v17.2s uaba v5.2s, v16.2s, v17.2s uaba v6.2s, v16.2s, v17.2s uaba v7.2s, v16.2s, v17.2s uaba v8.2s, v16.2s, v17.2s uaba v9.2s, v16.2s, v17.2s uaba v10.2s, v16.2s, v17.2s uaba v11.2s, v16.2s, v17.2s uaba v12.2s, v16.2s, v17.2s uaba v13.2s, v16.2s, v17.2s uaba v14.2s, v16.2s, v17.2s uaba v15.2s, v16.2s, v17.2s
movi v16.16b, 17 movi v17.16b, 18
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2502
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 37 | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache writeback (a8) | ac | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160204 | 40060 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 223 | 0 | 25 | 160117 | 100 | 160009 | 100 | 160020 | 500 | 2399187 | 1 | 40030 | 40048 | 40039 | 19977 | 6 | 19991 | 160120 | 200 | 160032 | 200 | 480096 | 40039 | 40049 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 10123 | 1 | 16 | 0 | 0 | 40045 | 0 | 160000 | 100 | 40040 | 40049 | 40040 | 40050 | 40041 |
160204 | 40039 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 39 | 0 | 25 | 160108 | 100 | 160008 | 100 | 160020 | 500 | 1280132 | 1 | 40021 | 40039 | 40049 | 19977 | 6 | 19999 | 160120 | 200 | 160032 | 202 | 480096 | 40039 | 40106 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 10118 | 0 | 16 | 0 | 0 | 40046 | 0 | 160000 | 100 | 40040 | 40040 | 40050 | 40050 | 40041 |
160204 | 40039 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 410 | 0 | 25 | 160117 | 100 | 160017 | 100 | 160020 | 500 | 2399131 | 1 | 40029 | 40039 | 40039 | 19977 | 6 | 19999 | 160120 | 200 | 160032 | 200 | 480096 | 40049 | 40049 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 10118 | 0 | 16 | 0 | 0 | 40046 | 0 | 160000 | 100 | 40049 | 40072 | 40040 | 40049 | 40072 |
160204 | 40048 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 30 | 0 | 25 | 160117 | 100 | 160008 | 100 | 160020 | 500 | 2399131 | 0 | 40020 | 40039 | 40048 | 19977 | 6 | 19990 | 160120 | 200 | 160032 | 200 | 480096 | 40048 | 40071 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 10118 | 0 | 16 | 0 | 0 | 40036 | 0 | 160000 | 100 | 40040 | 40040 | 40040 | 40040 | 40049 |
160204 | 40040 | 299 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 39 | 0 | 25 | 160108 | 100 | 160000 | 100 | 160000 | 500 | 1280000 | 0 | 40029 | 40039 | 40049 | 19973 | 3 | 20007 | 160100 | 200 | 160000 | 200 | 480000 | 40049 | 40039 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10110 | 1 | 16 | 1 | 1 | 40036 | 0 | 160000 | 100 | 40072 | 40040 | 40040 | 40050 | 40040 |
160204 | 40049 | 299 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 41 | 0 | 25 | 160117 | 100 | 160061 | 100 | 160000 | 500 | 2398999 | 0 | 40029 | 40039 | 40048 | 19973 | 3 | 19997 | 160100 | 200 | 160000 | 200 | 480000 | 40039 | 40039 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10110 | 1 | 16 | 1 | 1 | 40045 | 0 | 160000 | 100 | 40041 | 40040 | 40049 | 40049 | 40040 |
160204 | 40039 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 51 | 0 | 25 | 160100 | 100 | 160000 | 100 | 160000 | 500 | 2398999 | 1 | 40030 | 40048 | 40039 | 19973 | 3 | 19997 | 160100 | 200 | 160463 | 200 | 480000 | 40048 | 40048 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10110 | 1 | 16 | 1 | 1 | 40046 | 0 | 160000 | 100 | 40049 | 40072 | 40040 | 40040 | 40049 |
160204 | 40039 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 41 | 0 | 25 | 160100 | 100 | 160000 | 100 | 160000 | 500 | 1280000 | 1 | 40029 | 40071 | 40039 | 19973 | 3 | 19997 | 160100 | 200 | 160000 | 200 | 480000 | 40039 | 40048 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10110 | 1 | 16 | 1 | 1 | 40037 | 0 | 160000 | 100 | 40040 | 40040 | 40041 | 40040 | 40049 |
160204 | 40039 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 42 | 0 | 25 | 160100 | 100 | 160000 | 100 | 160000 | 500 | 1280000 | 0 | 40029 | 40049 | 40039 | 19973 | 3 | 20006 | 160100 | 200 | 160000 | 200 | 480000 | 40049 | 40039 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 0 | 10110 | 1 | 16 | 1 | 1 | 40036 | 0 | 160000 | 100 | 40072 | 40040 | 40040 | 40041 | 40040 |
160204 | 40049 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 41 | 0 | 25 | 160117 | 100 | 160017 | 100 | 160000 | 500 | 1280000 | 1 | 40020 | 40039 | 40039 | 19973 | 3 | 20006 | 160100 | 200 | 160000 | 200 | 480000 | 40039 | 40039 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10110 | 1 | 16 | 1 | 1 | 40036 | 0 | 160000 | 100 | 40050 | 40049 | 40040 | 40050 | 40050 |
Result (median cycles for code divided by count): 0.2503
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | l2 tlb miss instruction (0a) | 1e | 37 | 3a | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 5f | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160024 | 40049 | 300 | 2 | 0 | 0 | 17 | 0 | 56 | 25 | 160027 | 10 | 160017 | 10 | 160000 | 50 | 1319997 | 1 | 1 | 40020 | 40039 | 40039 | 19996 | 3 | 20020 | 160010 | 20 | 160000 | 20 | 480000 | 40048 | 40048 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10106 | 3 | 1 | 1 | 0 | 32 | 16 | 2 | 1 | 1 | 23 | 29 | 40036 | 0 | 20 | 9 | 160000 | 10 | 40049 | 40049 | 40040 | 40040 | 40049 |
160024 | 40048 | 300 | 0 | 0 | 0 | 17 | 0 | 75 | 25 | 160011 | 10 | 160001 | 10 | 160000 | 50 | 1319997 | 0 | 1 | 40021 | 40039 | 40048 | 19996 | 3 | 20028 | 160010 | 20 | 160000 | 20 | 480000 | 40039 | 40048 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10098 | 6 | 4 | 2 | 1 | 23 | 16 | 3 | 2 | 2 | 29 | 23 | 40045 | 0 | 41 | 13 | 160000 | 10 | 40049 | 40049 | 40049 | 40049 | 40050 |
160024 | 40048 | 300 | 1 | 1 | 0 | 34 | 1 | 75 | 25 | 160011 | 10 | 160017 | 10 | 160000 | 50 | 2398999 | 0 | 1 | 40020 | 40048 | 40048 | 19996 | 3 | 20020 | 160010 | 20 | 160000 | 20 | 480000 | 40040 | 40108 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10092 | 6 | 4 | 2 | 1 | 29 | 16 | 3 | 2 | 2 | 19 | 29 | 40045 | 0 | 41 | 14 | 160000 | 10 | 40049 | 40040 | 40040 | 40049 | 40049 |
160024 | 40048 | 299 | 1 | 0 | 0 | 17 | 0 | 84 | 25 | 160027 | 10 | 160017 | 10 | 160000 | 50 | 1319997 | 0 | 1 | 40029 | 40048 | 40040 | 19996 | 3 | 20019 | 160010 | 20 | 160000 | 20 | 480000 | 40040 | 40048 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10092 | 6 | 4 | 2 | 1 | 28 | 16 | 3 | 2 | 2 | 19 | 29 | 40045 | 0 | 41 | 18 | 160000 | 10 | 40049 | 40049 | 40049 | 40049 | 40049 |
160024 | 40048 | 300 | 1 | 0 | 0 | 17 | 0 | 90 | 25 | 160027 | 10 | 160017 | 10 | 160000 | 50 | 2398999 | 0 | 1 | 40030 | 40048 | 40048 | 19996 | 3 | 20028 | 160010 | 20 | 160000 | 20 | 480000 | 40048 | 40048 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10089 | 6 | 4 | 2 | 1 | 28 | 16 | 3 | 2 | 2 | 29 | 31 | 40045 | 0 | 41 | 13 | 160000 | 10 | 40049 | 40049 | 40049 | 40049 | 40049 |
160024 | 40040 | 299 | 1 | 0 | 0 | 17 | 0 | 1242 | 25 | 160011 | 10 | 160001 | 10 | 160000 | 50 | 1319997 | 0 | 1 | 40029 | 40048 | 40040 | 19996 | 3 | 20020 | 160123 | 20 | 160000 | 20 | 480000 | 40048 | 40048 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10092 | 6 | 4 | 2 | 1 | 30 | 16 | 3 | 2 | 2 | 31 | 18 | 40036 | 0 | 41 | 15 | 160000 | 10 | 40041 | 40049 | 40041 | 40040 | 40041 |
160024 | 40040 | 300 | 1 | 0 | 0 | 17 | 0 | 76 | 25 | 160027 | 10 | 160017 | 10 | 160000 | 50 | 2398999 | 0 | 1 | 40029 | 40048 | 40048 | 19996 | 3 | 20028 | 160010 | 20 | 160000 | 20 | 480000 | 40048 | 40048 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10090 | 6 | 4 | 2 | 1 | 28 | 16 | 3 | 2 | 2 | 28 | 29 | 40036 | 0 | 41 | 18 | 160000 | 10 | 40049 | 40049 | 40049 | 40049 | 40049 |
160024 | 40039 | 300 | 1 | 0 | 0 | 17 | 0 | 90 | 25 | 160011 | 10 | 160001 | 10 | 160000 | 50 | 2398999 | 0 | 1 | 40020 | 40048 | 40048 | 19996 | 3 | 20028 | 160010 | 20 | 160469 | 20 | 480000 | 40048 | 40107 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10071 | 6 | 4 | 2 | 1 | 31 | 16 | 3 | 2 | 2 | 30 | 30 | 40045 | 0 | 41 | 15 | 160000 | 10 | 40041 | 40049 | 40041 | 40040 | 40049 |
160024 | 40048 | 300 | 1 | 0 | 0 | 17 | 0 | 84 | 25 | 160027 | 10 | 160017 | 10 | 160000 | 50 | 2398999 | 0 | 1 | 40021 | 40040 | 40040 | 19996 | 3 | 20028 | 160010 | 20 | 160000 | 20 | 480000 | 40048 | 40048 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10090 | 6 | 4 | 2 | 1 | 18 | 16 | 3 | 2 | 2 | 30 | 18 | 40045 | 0 | 41 | 18 | 160000 | 10 | 40049 | 40040 | 40049 | 40040 | 40040 |
160024 | 40048 | 300 | 1 | 0 | 0 | 1 | 1 | 90 | 25 | 160011 | 10 | 160017 | 10 | 160000 | 50 | 1280000 | 0 | 1 | 40021 | 40039 | 40048 | 19996 | 3 | 20019 | 160010 | 20 | 160000 | 20 | 480000 | 40048 | 40048 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 0 | 10091 | 6 | 4 | 2 | 1 | 31 | 16 | 3 | 2 | 2 | 33 | 19 | 40037 | 0 | 41 | 15 | 160000 | 10 | 40041 | 40040 | 40049 | 40041 | 40049 |