Firestorm: UABA (vector, 4H) measurements

Code:

  uaba v0.4h, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	10	0	2	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	82	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	571	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	33	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	3	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  uaba v0.4h, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	82	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30132	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4278670	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	3	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	9	0	640	3	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30516	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30085
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	17	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  uaba v0.4h, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30229	226	1	1	0	82	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30086	30038	30038
10204	30037	225	0	0	0	2159	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	147	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30227	30038	30038	30086
10204	30037	224	0	0	18	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	1	0	1	2	733	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	644	8	16	11	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	644	10	16	15	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	644	11	16	10	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	2	89	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	644	10	16	11	11	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	644	11	16	5	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	644	10	16	10	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	644	10	16	10	9	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	2	131	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	644	10	16	5	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	644	11	16	10	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	644	10	16	10	10	29630	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  uaba v0.4h, v1.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	2	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	623	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10025	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	82	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  uaba v0.4h, v8.4h, v9.4h
  movi v1.16b, 0
  uaba v1.4h, v8.4h, v9.4h
  movi v2.16b, 0
  uaba v2.4h, v8.4h, v9.4h
  movi v3.16b, 0
  uaba v3.4h, v8.4h, v9.4h
  movi v4.16b, 0
  uaba v4.4h, v8.4h, v9.4h
  movi v5.16b, 0
  uaba v5.4h, v8.4h, v9.4h
  movi v6.16b, 0
  uaba v6.4h, v8.4h, v9.4h
  movi v7.16b, 0
  uaba v7.4h, v8.4h, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10111	2	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	474	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10111	3	16	1	1	20061	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20087	150	1	0	0	0	0	0	3	75	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10053	84	2	1	28	25	2	1	2	24	27	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	0	0	0	0	0	3	455	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10049	71	2	1	25	25	2	1	1	23	23	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	0	0	3	75	27	80012	12	80000	12	80000	62	640916	1	1	5	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10046	68	2	1	26	25	2	1	1	19	22	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	0	0	0	0	0	3	75	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10052	71	2	1	23	25	2	1	1	25	21	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	0	0	0	0	0	3	75	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10046	77	2	1	21	25	2	1	1	23	23	20048	2	20	1	160000	10	20052	20052	20052	20052	20293
160024	20051	151	1	0	0	0	0	0	3	740	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	3	10050	74	2	1	23	25	2	1	1	20	23	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	0	0	0	0	0	3	75	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10051	71	2	1	24	25	2	1	1	23	23	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	151	1	0	1	0	0	0	3	75	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10046	74	2	1	24	25	2	1	1	14	26	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	0	0	0	0	0	3	75	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10049	74	2	1	24	25	2	1	1	29	22	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	0	0	0	159	0	3	170	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20213	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10051	72	2	1	23	25	2	1	1	26	21	20048	2	20	1	160000	10	20052	20052	20052	20052	20052

Test 6: throughput

Count: 16

Code:

  uaba v0.4h, v16.4h, v17.4h
  uaba v1.4h, v16.4h, v17.4h
  uaba v2.4h, v16.4h, v17.4h
  uaba v3.4h, v16.4h, v17.4h
  uaba v4.4h, v16.4h, v17.4h
  uaba v5.4h, v16.4h, v17.4h
  uaba v6.4h, v16.4h, v17.4h
  uaba v7.4h, v16.4h, v17.4h
  uaba v8.4h, v16.4h, v17.4h
  uaba v9.4h, v16.4h, v17.4h
  uaba v10.4h, v16.4h, v17.4h
  uaba v11.4h, v16.4h, v17.4h
  uaba v12.4h, v16.4h, v17.4h
  uaba v13.4h, v16.4h, v17.4h
  uaba v14.4h, v16.4h, v17.4h
  uaba v15.4h, v16.4h, v17.4h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40048	300	0	1	0	1	0	0	0	0	0	17	2	49	25	160117	100	160017	100	160000	500	1280000	40029	40039	40048	19973	0	3	20006	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	14	16	14	14	40045	160000	100	40040	40049	40040	40049	40040
160204	40039	300	0	1	0	1	0	0	0	0	0	0	2	166	25	160100	100	160000	100	160000	500	1280000	40020	40039	40048	19973	0	3	20006	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	12	16	14	12	40036	160000	100	40040	40049	40040	40049	40041
160204	40048	300	0	1	0	1	0	0	0	12	0	0	2	69	25	160117	100	160001	100	160000	500	2398999	40020	40039	40048	19973	0	3	20007	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	13	16	13	14	40036	160000	100	40049	40040	40041	40040	40049
160204	40049	300	0	1	0	1	0	0	0	0	0	17	2	57	25	160117	100	160017	100	160000	500	2398999	40029	40048	40048	19973	0	3	20006	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	14	16	13	14	40036	160000	100	40040	40041	40040	40050	40040
160204	40039	300	0	1	0	1	0	0	0	0	0	1	2	58	25	160117	100	160065	100	160000	500	2398999	40030	40039	40039	19973	0	3	20006	160100	200	160000	200	480000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	2	10114	6	16	8	16	40045	160000	100	40040	40049	40040	40040	40049
160204	40048	300	0	1	0	1	0	0	0	0	0	0	2	523	25	160117	100	160017	100	160000	500	1319998	40029	40039	40039	19973	0	3	19997	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	13	16	12	14	40045	160000	100	40040	40049	40040	40040	40040
160204	40039	300	0	1	0	1	0	0	0	21	0	0	2	48	25	160101	100	160000	100	160000	500	1280000	40020	40039	40039	19973	0	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	14	16	14	14	40036	160000	100	40040	40040	40049	40040	40040
160204	40039	300	0	1	0	1	0	0	0	0	0	17	2	48	25	160117	100	160017	100	160000	500	2399055	40020	40048	40039	19973	0	3	19997	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	12	16	14	14	40036	160000	100	40050	40040	40040	40040	40050
160204	40039	300	0	1	0	1	0	0	0	0	0	17	2	48	25	160117	100	160017	100	160000	500	1280000	40020	40039	40048	19973	0	3	20006	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	14	16	14	15	40036	160000	100	40040	40102	40049	40040	40040
160204	40039	300	0	1	0	1	0	0	0	0	0	17	2	922	25	160117	100	160000	100	160000	500	1280000	40020	40048	40039	19973	0	3	19997	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	12	16	14	12	40036	160000	100	40049	40040	40049	40040	40049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	300	0	0	0	0	0	53	0	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	6	16	2	1	1	8	8	40045	0	20	6	160000	10	40040	40049	40040	40040	40110
160024	40039	299	0	0	0	0	0	52	0	25	160027	10	160001	10	160000	50	1280000	1	1	40020	40040	40039	19996	3	20019	160010	20	160000	20	480000	40039	40049	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	4	16	4	1	2	6	6	40036	0	20	6	160000	10	40040	40040	40040	40072	40040
160024	40039	300	0	0	9	0	0	46	0	25	160027	10	160000	10	160000	50	2399082	1	1	40020	40039	40048	19996	3	20019	160010	20	160000	20	480000	40039	40051	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	5	16	2	1	1	4	7	40036	0	20	6	160000	10	40040	40040	40040	40072	40040
160024	40039	300	0	0	0	0	0	46	0	25	160071	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	3	10022	3	1	1	7	16	2	1	1	4	5	40036	0	20	18	160000	10	40049	40040	40040	40040	40040
160024	40039	300	0	0	0	0	17	55	0	25	160010	10	160000	10	160000	50	2398999	1	1	40020	40039	40071	19996	3	20028	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	2	7	16	2	1	1	5	3	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	1	40029	40048	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	4	16	2	2	1	7	4	40036	0	20	6	160000	10	40072	40040	40072	40040	40040
160024	40071	299	0	0	0	0	0	46	0	25	160010	10	160001	10	160000	50	1280000	0	1	40052	40039	40039	19996	3	20020	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10024	6	1	2	5	16	4	2	2	7	7	40036	0	40	12	160000	10	40040	40040	40072	40040	40040
160024	40039	300	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20020	160010	20	160000	20	480000	40039	40071	1	1	160021	10	9	10	10	160000	10	0	0	10022	6	2	2	5	16	4	1	1	5	3	40045	0	20	14	160000	10	40041	40050	40040	40040	40040
160024	40048	300	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20051	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	2	2	5	16	4	2	2	5	5	40046	0	20	9	160000	10	40040	40041	40040	40072	40040
160024	40039	300	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10024	6	1	1	5	16	2	2	1	8	4	40068	0	20	6	160000	10	40040	40040	40040	40040	40040

UABA (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations