Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UABA (vector, 4S)

Test 1: uops

Code:

  uaba v0.4s, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722061254825100010001000398313301830373037241532895100010003000303730371110011000003373116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
1004303722016825482510001000100039831330183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010003000303730371110011000054073116112630100030383038303830383038
1004303722061254825100010001000398313301830373037241532895100010003000303730371110011000032073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100030003037303711100110000122073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  uaba v0.4s, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000612954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000071012162229634100001003003830038300383003830038
102043003722400007262954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071002162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071012162229634100001003003830038300383003830038
102043003722400007262954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071012162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071013162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071012162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071012162229634100001003003830038300383003830038
1020430037225001805362954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071012162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071012162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000071012162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100010640216332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316422963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130162300373008428287328767100102010000203000030084300371110021109101010000100000640316332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316322963010000103003830038300383003830038
10024300372241806129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130126300373003728287328767100102010000203000030037300371110021109101010000100000640216332963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  uaba v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745102562001000020030000300373003711102011009910010010000100000000000710011611296340100001003003830038300383003830038
10204300372240006006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000600710011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000600710011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030531300373003711102011009910010010000100000000000710011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373008311102011009910010010000100000000000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000640241222963010000103003830038300853003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000101200640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300831110021109101010000100000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  uaba v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722406129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722406129548251010011210000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548441010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250002622954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000644111611112963010000103003830038300383003830038
1002430037225036026229548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110022109101010000100006441016582963010000103003830038300383003830038
10024300372250002622954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000644101610102963010000103003830038300383003830038
10024300372250002622954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000644111611102963010000103003830038300383003830038
10024300372250602622954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000644101610102963010000103003830038300383003830038
10024300372250002622954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000644111610102963010000103003830038300383003830038
10024300372250002622954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000644121610102963010000103003830038300383003830038
10024300372250002622954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000644816852963010000103003830038300383003830038
10024300372240002622954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010001644101611112963010000103003830038300383003830038
1002430037225000262295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000164481610102963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  uaba v0.4s, v8.4s, v9.4s
  movi v1.16b, 0
  uaba v1.4s, v8.4s, v9.4s
  movi v2.16b, 0
  uaba v2.4s, v8.4s, v9.4s
  movi v3.16b, 0
  uaba v3.4s, v8.4s, v9.4s
  movi v4.16b, 0
  uaba v4.4s, v8.4s, v9.4s
  movi v5.16b, 0
  uaba v5.4s, v8.4s, v9.4s
  movi v6.16b, 0
  uaba v6.4s, v8.4s, v9.4s
  movi v7.16b, 0
  uaba v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042007615000003925801001008000010080000500640000120045020064200643228010020080000200240000200642006411160201100991001001600001000000010111116112006101600001002006520065200652006520065
1602042006415100003925801001008000010080000500640000120045020064200643228010020080000200240000200642006411160201100991001001600001000000010111116112006101600001002006520065200652006520065
160204200641500000392580100100800001008000050064000012004502006420064322801002008000020024000020064200641116020110099100100160000100004050710111116112006101600001002006520147201462006520065
1602042006415000003925801001008000010080000500640000120045020064200643228010020080000200240000200642006411160201100991001001600001000010010111116112006101600001002006520065200652030520065
1602042006415000003925801001008000010080000500640000120111020064200643228010020080000200240000200642006411160201100991001001600001000000010111116112006101600001002006520065200652006520065
1602042006415000003925801001008000010080000500640000020045020064200643228010020080000200240000200642006411160201100991001001600001000000010111116112006101600001002006520065200652006520065
1602042006415000003925801001008000010080000500640000120045020064200643228010020080000200240000200642006411160201100991001001600001000000010111116112006101600001002006520065200652006520065
1602042006415100003925801001008000010080000500640000120045020064200643228010020080000200240000200642006411160201100991001001600001000000010111116112006101600001002023020065200652006520065
1602042006415000003925801001008000010080000500640000120045020064200643228010020080000200240000200642006411160201100991001001600001000000010111116112006101600001002006520065200652006520065
1602042006415000003925801001008000010080000500640000020045020064200643228010020080000200240000200642006411160201100991001001600001000000010111116112006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

retire uop (01)cycle (02)03mmu table walk instruction (07)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200711500004527800121280000128000062640000010201702006020060322800122080000202400002006020062111600211091010160000100000010032112173421179200592401160000102015320052200632005220063
160024200511510004527800121280000128000062640000015200432006020062322800122080000202400002006020060111600211091010160000100000010033114263432267200572402160000102006120063200632022320061
160024200601500005129800121280000128000062640000015200432006220062322800122080000202400002006020060111600211091010160000100000010034114273642276200572412160000102006320063200612006120061
16002420062150000512980012128000012800006264000001520041200602006032280012208000020240000200602006011160021109101016000010000049010034114273442267200572402160000102006320061200632006320063
160024200621500005129800121280000128000062640000015200432006020060322800122080000202400002006220060111600211091010160000100000310032114273642276200572402160000102006120061200612006120063
16002420062151000512980012128000012800006264000001520043200622006232280012208000020240000200622006011160021109101016000010000001003384162532277200572402160000102006120061200632005220052
160024200511500005129800121280000128000062640000015200432006020060322800122080000202400002006020060111600211091010160000100000010033114273442266200592402160000102006320063200612006129339
160024200621500005129800121280000128000062640000115200412006220062322800122080000202400002006220060111600211091010160000100000010034114273642267200592402160000102006120061200612006120061
160024200601500005129800121280000128000062640000015200432006020060322800122080000202400002006020060111600211091010160000100000010034114293432286200592402160000102006320063200612006120063
160024200601500005129800121280000128000062640000015200432006020060322800122080000202400002006020062111600211091010160000100000010033114293642286200572412160000102006120061200612006320061

Test 6: throughput

Count: 16

Code:

  uaba v0.4s, v16.4s, v17.4s
  uaba v1.4s, v16.4s, v17.4s
  uaba v2.4s, v16.4s, v17.4s
  uaba v3.4s, v16.4s, v17.4s
  uaba v4.4s, v16.4s, v17.4s
  uaba v5.4s, v16.4s, v17.4s
  uaba v6.4s, v16.4s, v17.4s
  uaba v7.4s, v16.4s, v17.4s
  uaba v8.4s, v16.4s, v17.4s
  uaba v9.4s, v16.4s, v17.4s
  uaba v10.4s, v16.4s, v17.4s
  uaba v11.4s, v16.4s, v17.4s
  uaba v12.4s, v16.4s, v17.4s
  uaba v13.4s, v16.4s, v17.4s
  uaba v14.4s, v16.4s, v17.4s
  uaba v15.4s, v16.4s, v17.4s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)373a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440067300110248025160100100160000100160000500128000014002040048400481997332000616010020016000020048000040039400391116020110099100100160000100001011413161414400361600001004004940040400494004040049
160204400483001117257025160100100160000100160000500239899914002940039400391997331999716010020016000020048000040048400391116020110099100100160000100001011411161414400451600001004004940040400494004040050
16020440039300111724802516011710016001710016000050013199971400204003940048199733200061601002001600002004800004004840039111602011009910010016000010000101148161514400361600001004004040041400494004040049
16020440048300110248025160100100160000100160000500239899904002940048400481997332000616010020016000020048000040049400391116020110099100100160000100001011414161512400371600001004004040049400404004940040
160204400393001102238025160100100160000100160000500128000004002940049400491997332000616010020016000020048000040048400391116020110099100100160000100001011414161514400451600001004004040040400494004040040
16020440039300110299025160100100160000100160000500239899904002040039400401997331999716010020016000020048000040048400391116020110099100100160000100001011414161313400361600001004004940040400494004040050
160204400393001117257025160117100160000100160000500239899904002040039400481997332000616010020016000020048000040039400481116020110099100100160000100001011414161414400361600001004004940040400494004040049
16020440048300110248025160100100160000100160000500239899904002040039400481997332000616010020016000020048000040039400521116020110099100100160000100001011414161212400361600001004005340040400404004040049
160204400392991117257025160117100160017100160000500128000004002040048400391997331999816010020016000020048000040039400391116020110099100100160000100001011414161514400361600001004004940040400494004040040
160204400393001117257025160100100160017100160000500239899914003040039400391997332000616010020016000020048000040039400481116020110099100100160000100001011413261414400361600001004004040053400404004940040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)1e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440049299000055025160027101600171016000050128000011400290400484003919996320028160010201600002048000040039400391116002110910101600001000001002231151621144400450207160000104004040041400404004040040
160024400403000001746025160027101600011016000050239899911400200400394004819996320019160010201600002048000040048400391116002110910101600001000001002231141621144400360206160000104004040041400494004040040
160024400482990001755025160010101600001016000050128000011400210400494003919996320019160010201600002048000040040400391116002110910101600001000001002231141621144400360206160000104004040041400404004040049
16002440039300000156025160010101600001016000050128000011400200400484003919996320019160010201600002048000040049400391116002110910101600001010001002231131621134400360207160000104005040040400494004040040
16002440039300000047025160027101600171016000050128000001400290400394004819996320019160010201600002048000040039400391116002110910101600001000001002231141621132400360209160000104004940049400414004040040
160024400393000000520251600271016000010160000501280000114002004004840039199963200191600102016000020480000400404003911160021109101016000010000010022322316422344003604012160000104004040049400404004040040
16002440039300000053025160010101600001016000050128000011400290400394003919996320019160010201600002048000040040400491116002110910101600001000001002231141621143400370206160000104004040040400404004940040
1600244003930000017520251600101016000010160000502398999014002004004040039199963200191600102016000020480000400394003911160021109101016000010000010022311416412554003604018160000104004940040400414004040049
16002440048300000052025160010101600001016000050128000011400200400394003919996320020160010201600002048000040048400391116002110910101600001000001002462141622167400360206160000104004040041400404004040040
1600244004029900017470251600271016001710160000501280000014002904003940048199963200281600102016000020480000400394003911160021109101016000010000010024622516422554004504012160000104004040050400404004940049