Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UABDL2 (vector, 4S)

Test 1: uops

Code:

  uabdl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037231032548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723612548251000100010003983131301830373037241532895100010002000303730371110011000088116112630100030383038303830383038
1004303723612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303722612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  uabdl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224000000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000000822954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000000612954825101231001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240000007262952925101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110202100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250441295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250156295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037224061295482510010101000010100005042773131300183003730037282873287671001020100002020658300373003721100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uabdl2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001611297060100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722505042954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010680126402162229630010000103003830038300383003830038
100243003722500008629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000023329548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722400006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uabdl2 v0.4s, v8.8h, v9.8h
  uabdl2 v1.4s, v8.8h, v9.8h
  uabdl2 v2.4s, v8.8h, v9.8h
  uabdl2 v3.4s, v8.8h, v9.8h
  uabdl2 v4.4s, v8.8h, v9.8h
  uabdl2 v5.4s, v8.8h, v9.8h
  uabdl2 v6.4s, v8.8h, v9.8h
  uabdl2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005715000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511031611200360800001002004020040200402004020040
802042003915000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000010511011611200360800001002004020040200402004020040
802042003915000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
802042003915000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
8020420039150000041618010010380000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000036511011611200360800001002004020040200402004020040
802042003915000005162580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000111511011611200360800001002004020040200402004020040
802042003915000304125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
802042003915000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
802042003915000004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
802042003915000004125801001008009710080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481504025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000050203160112003680000102004020040200402004020040
80024200391504025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000050201160112003680000102004020040200402004020040
80024200391504025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000050201160112003680000102004020040200402004020040
80024200391504025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000050201160112003680000102004020040200402004020040
80024200391504025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010201050201160112003680000102004020040200402004020040
800242003915040258001010800001080000506400001200200200392003999963100198001020800002016000020039200391180021109101080000100003350201160112003680000102004020040200402004020040
80024200391508625800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000050201160112003680000102004020040200402004020040
80024200391504025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010001050201160112003680000102004020040200402004020040
80024200391504025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010000050201160112003680000102004020040200402004020040
80024200391504025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010001650201160112003680000102004020040200402004020040