Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UABDL2 (vector, 8H)

Test 1: uops

Code:

  uabdl2 v0.8h, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220010525482510081000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000105039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723008225482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230012425482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723008225482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  uabdl2 v0.8h, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282659287621010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000990061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006403162229630010000103003830038300383003830038
10024300372250000045600726295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000510061295482510010101000010100005042773131300183003730037282918287871001020100002020000300843003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000061295482510010101000010100007142773131300183003730037283003287671001020100002020000300373003711100211091010100001000000007272162229630010000103003830038300383003830038
1002430037225000005430061295482510010101000012100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000306402162229630010000103003830038300383003830038
100243003722500000270061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000002006403242229702010000103003830038300383003830038
1002430037225000006108061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000306402162229630010000103003830038300383003830228
100243003722500000000103295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000010006402162229630010000103003830038300383003830038
100243003722400000000103295482510010101001610100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402402229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uabdl2 v0.8h, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000528006129548251010010010000100100005004277313130018030037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830079
1020430037225000120006129548251010010010000100100005004277313130018030037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000450006129548251010010010000100100005004277313030018030037300372826532874510100200100002042000030037300371110201100991001001000010000000071011601296340100001003003830038300383003830038
1020430037225000384006129548251010010010000100100005004277313130018030037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000348006129548251010010010000100100005004277313130018030037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000438006129548251010010010000100100005004277313130018030037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000114006129548251010010010000100100005004277313130018030037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500069006129548251010010010000100100005004277313130018030037300372826532874510100200100002002000030037300371110201100991001001000010000090071011611296340100001003003830038300383003830038
1020430037225000108006129548251010010010000100100005004277313130018030037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018030037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225039361295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316222963010000103003830038300383003830038
1002430037225046861295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250174413295482510010101000010100005542773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225048061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225052261295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225051661295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250061295032510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225054961295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225041461295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225054661295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uabdl2 v0.8h, v8.16b, v9.16b
  uabdl2 v1.8h, v8.16b, v9.16b
  uabdl2 v2.8h, v8.16b, v9.16b
  uabdl2 v3.8h, v8.16b, v9.16b
  uabdl2 v4.8h, v8.16b, v9.16b
  uabdl2 v5.8h, v8.16b, v9.16b
  uabdl2 v6.8h, v8.16b, v9.16b
  uabdl2 v7.8h, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581509041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000151102161120036800001002004020040200402004020040
802042003915018041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002005020040200402004020040
80204200391506041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010010051101161120036800001002004020040200402004020040
80204200391500078258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915012041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150393041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200401500040258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100000502021602220036080000102004020040200402004020040
80024200391500040258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100000502021602220036080000102004020040200402004020040
8002420039150022540258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100000502021602220036080000102004020040200402004020040
80024200391500040258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100000502021602220036080000102004020040200402004020040
80024200391500040258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100003502041612220036080000102004020040200402004020040
800242003915000135258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100000502021602220036080000102004020040200402004020040
800242003915001540258001010800001080000506400001120020200392003999963100198001020800002016000020039200391180021109101080000100000502021602220036080000102004020040200402004020040
800242003915001540258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100000502021602220036080000102004020040200402004020040
80024200391500340258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100010502021602220036080000102004020040200402004020040
80024200391500640258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100000502021602220036080000102004020040200402004020040