Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UABD (vector, 4S)

Test 1: uops

Code:

  uabd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372396125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372308425482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
1004303723015625482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372206125482510001000100039831313018303730372415628951000100020003037303711100110000073216222630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372308425482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  uabd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500145295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007102163329634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
102043003722500189295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
102043003722500753295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
102043003722513288103295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001002221007102162229634100001003003830038300383003830038
102043003722500834295484610135100100001001000050042773131300183003730037282653287451010020010000200200003003730037211020110099100100100001000000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
102043003722500168295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000037102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240000233295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316352963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830086300383008530038
1002430037237000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316342963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316342963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316342963010000103003830038300383003830038
1002430037224000082295482510010101000010100005042777973001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250000441295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316342963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uabd v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
1020430037224000612954844101371111000010010298500427731330018300843013228267132878110260204100002002000030178300841110201100991001001000010000007102352229634100001003003830038300383003830038
1020430037225220774295484510124116100081231014950042773133001830037300372826532874510265200100002002000030037300371110201100991001001000010000563507102162229703100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100001507102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
102043003722400061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030183300371110201100991001001000010000007102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002020000300843003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001040640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uabd v0.4s, v8.4s, v9.4s
  uabd v1.4s, v8.4s, v9.4s
  uabd v2.4s, v8.4s, v9.4s
  uabd v3.4s, v8.4s, v9.4s
  uabd v4.4s, v8.4s, v9.4s
  uabd v5.4s, v8.4s, v9.4s
  uabd v6.4s, v8.4s, v9.4s
  uabd v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150004125801001008000011680000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051102162120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051102162320036800001002004020040200402004020040
8020420039150006225801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051103163220036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999738100228010020080000200160210200392003911802011009910010080000100200473051102161220036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000020051102163220036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051102163220036800001002004020040200402004020040
8020420039150008325801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051103163320036800001002004020040200402004020040
8020420039150008325801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051103163220036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000251103163220036800001002004020040200402004020040
8020420039150106243801001008000010080000500640000020020200392003999733999780100200800002001600002003920039418020110099100100800001000003051103163320036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)091e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9branch cond mispred nonspec (c5)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420040150000040258001010800001280000606400000020020200392003999963100198001220800002016000020039200391180021109101080000100000502001161120036080000102004020040200402004020040
8002420039150010040258001010800001080000506400000120020200392003999963100198001220800002016000020039200391180021109101080000100000502001161120036080000102004020040200402004020040
8002420039150000040258001010800001280000506400000020020200392003999963100198001220800002016000020039200391180021109101080000100000502003161120036080000102004020040200402004020040
8002420039150000140258001010800001080000506400000020020200392003999963100198001220800002016000020039200391180021109101080000100000502001161120036080000102004020040200402004020040
8002420039150000040258001010800001080000506400000020020200392003999963100198001220800002016000020039200391180021109101080000100000502001161120036080000102004020040200402004020040
80024200391500000230258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000502003161120036080000102004020040200402004020040
8002420039150000040258001010800001080000506400000020020200392003999963100198001220800002016000020039200391180021109101080000100000502001161120036080000102004020040200402004020040
8002420039150000040258001010800001080000506400000020020200392003999963100198001220800002016000020039200391180021109101080000100000502001166220036080000102004020040200402004020040
8002420039150000040258001010800001080000506400000020020200392003999963100198001220800002016000020039200391180021109101080000100000502013161220036080000102004020040200402004020040
8002420039150000043258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000502001161120036080000102004020040200402004020040