Firestorm: UADALP (vector, 2D) measurements

Code:

  uadalp v0.2d, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2702	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  uadalp v0.2d, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29539	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	6	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	105	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	536	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	726	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	726	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	17	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  uadalp v0.2d, v0.4s

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	9	0	315	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	832	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	276	0	965	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	874	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	2	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	149	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	223	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	987	29547	25	10100	100	10000	100	10000	560	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	564	1	907	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	1	1	1	717	0	16	0	2	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	985	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	1	1	1	717	0	16	0	0	29714	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	105	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	27	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	54	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	103	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	0	0	640	2	16	2	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	17	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	82	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	84	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	147	29547	25	10010	10	10000	10	10000	50	4277160	30018	30224	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uadalp v0.2d, v8.4s
  movi v1.16b, 0
  uadalp v1.2d, v8.4s
  movi v2.16b, 0
  uadalp v2.2d, v8.4s
  movi v3.16b, 0
  uadalp v3.2d, v8.4s
  movi v4.16b, 0
  uadalp v4.2d, v8.4s
  movi v5.16b, 0
  uadalp v5.2d, v8.4s
  movi v6.16b, 0
  uadalp v6.2d, v8.4s
  movi v7.16b, 0
  uadalp v7.2d, v8.4s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2510

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	150	4	2	3	57	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10136	11	16	13	11	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	3	3	4	57	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10135	15	16	11	8	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	5	5	4	57	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10134	14	16	14	14	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	3	3	3	57	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10135	14	16	13	8	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	3	3	4	99	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10136	14	16	13	14	20062	160000	100	20066	20169	20160	20066	20066
160204	20065	150	2	3	3	78	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10135	10	16	13	8	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	4	3	4	120	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10134	13	16	13	8	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	1	3	4	185	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10127	13	16	12	17	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	5	5	3	122	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10136	13	16	14	8	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	3	3	4	57	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10136	11	16	15	13	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20087	150	0	9	0	51	29	80010	10	80000	10	80000	50	640000	1	1	20041	20051	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10028	6	2	2	11	25	4	2	2	5	2	20057	40	1	160000	10	20061	20052	20061	20061	20061
160024	20051	150	0	6	0	95	27	80010	10	80000	10	80000	50	640000	1	1	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10031	6	2	2	9	34	4	2	2	9	3	20057	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	0	51	27	80010	10	80000	10	80000	50	640000	1	1	20041	20051	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	1	3	0	0	10031	6	2	2	3	34	4	1	2	3	10	20057	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	12	0	45	29	80010	10	80000	10	80000	50	640000	0	0	20041	20060	20051	3	22	80010	20	80000	20	160212	20133	20060	2	1	160021	10	9	10	10	160000	10	0	6	0	0	10031	6	2	1	3	25	4	2	2	9	8	20057	20	2	160000	10	20061	20061	20061	20052	20052
160024	20060	150	0	0	0	74	29	80010	10	80000	10	80000	50	640000	0	0	20041	20060	20051	3	22	80010	20	80000	20	160000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10028	6	1	2	5	25	4	2	2	3	13	20057	40	2	160000	10	20052	20061	20061	20052	20061
160024	20051	150	0	0	0	72	27	80010	10	80000	10	80000	50	640000	0	0	20041	20051	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10031	6	2	2	9	25	4	2	2	5	7	20048	20	2	160000	10	20061	20061	20061	20052	20052
160024	20060	150	0	0	0	89	27	80010	10	80000	10	80000	50	640000	0	0	20041	20060	20060	3	22	80010	20	80000	20	160000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10028	6	2	1	4	34	4	2	2	4	6	20057	20	2	160000	10	20061	20052	20061	20061	20061
160024	20060	150	0	12	0	116	29	80010	10	80000	10	80000	50	640000	1	0	20041	20051	20051	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10031	3	2	2	6	34	4	1	1	5	6	20057	40	2	160000	10	20052	20052	20061	20052	20061
160024	20138	150	0	30	0	51	27	80010	10	80000	10	80000	50	640000	0	0	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10031	6	2	2	6	25	4	1	2	4	5	20057	20	2	160000	10	20052	20061	20052	20061	20052
160024	20051	150	0	0	0	592	27	80010	10	80000	10	80000	50	640000	0	0	20032	20060	20051	3	22	80010	20	80000	20	160000	20060	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10035	6	1	2	9	25	4	2	1	3	14	20048	40	1	160000	10	20061	20061	20052	20052	20061

Test 5: throughput

Count: 16

Code:

  uadalp v0.2d, v16.4s
  uadalp v1.2d, v16.4s
  uadalp v2.2d, v16.4s
  uadalp v3.2d, v16.4s
  uadalp v4.2d, v16.4s
  uadalp v5.2d, v16.4s
  uadalp v6.2d, v16.4s
  uadalp v7.2d, v16.4s
  uadalp v8.2d, v16.4s
  uadalp v9.2d, v16.4s
  uadalp v10.2d, v16.4s
  uadalp v11.2d, v16.4s
  uadalp v12.2d, v16.4s
  uadalp v13.2d, v16.4s
  uadalp v14.2d, v16.4s
  uadalp v15.2d, v16.4s

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40073	300	0	891	0	0	30	0	25	160108	100	160008	100	160020	500	2399131	1	40020	40039	40048	19993	0	6	19999	160120	200	160032	200	320064	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	2	16	2	2	40046	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	618	0	0	30	0	25	160108	100	160008	100	160020	500	1280132	1	40020	40048	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	2	16	2	2	40036	160000	100	40040	40049	40040	40040	40040
160204	40039	300	0	711	0	17	30	0	25	160108	100	160008	100	160020	500	1280132	1	40029	40039	40039	19977	7	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	3	16	3	3	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	720	0	17	410	0	25	160108	100	160008	100	160020	500	2399131	1	40020	40048	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	2	16	2	2	40036	160000	100	40040	40049	40040	40040	40040
160204	40048	300	0	675	0	17	39	0	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	0	6	19999	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	2	16	2	2	40036	160000	100	40049	40040	40049	40040	40040
160204	40039	300	0	720	0	0	30	0	25	160117	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	0	6	19999	160120	200	160032	200	320064	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	2	16	2	2	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	480	0	0	39	0	25	160117	100	160017	100	160020	500	1280132	1	40029	40048	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10134	2	16	2	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	147	0	0	30	0	25	160117	100	160008	100	160020	500	1280132	1	40020	40048	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	2	16	2	2	40045	160000	100	40049	40040	40049	40040	40040
160204	40048	300	0	603	0	0	30	0	50	160108	100	160017	100	160020	500	1280132	1	40020	40048	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	2	16	2	2	40036	160000	100	40040	40040	40040	40040	40049
160204	40039	300	0	627	0	0	30	0	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40048	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	2	16	2	2	40036	160000	100	40040	40040	40053	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40059	299	0	0	0	0	1	0	0	0	17	47	0	25	160027	10	160000	10	160000	50	2399027	1	1	0	40030	40040	40048	19996	3	20020	160010	20	160000	20	320000	40039	40049	1	1	160021	10	9	10	10	160000	10	2	0	0	0	1	0	4613	2	0	10139	3	2	1	9	131	2	1	1	6	7	40176	20	6	160000	10	40573	40634	40661	40661	40648
160024	40670	305	1	1	0	1	10	10	930	880	104	1943	145	98	161179	10	161120	10	161247	50	2017233	1	1	0	40558	40664	40712	20105	53	20325	161307	20	161174	20	322284	40640	40519	6	1	160021	10	9	10	10	160000	10	2	0	0	0	0	2	5013	2	0	10173	3	1	2	5	78	2	1	2	4	7	40564	20	8	160000	10	40597	40703	40648	40578	40715
160024	40670	305	0	0	0	1	11	10	1194	880	99	1209	124	193	161111	12	161185	10	161507	50	2524536	1	1	0	40551	40829	40766	20157	59	20394	161826	22	160583	20	323242	40783	40755	13	1	160021	10	9	10	10	160000	10	2	0	0	1	1	4	6280	0	0	10186	3	1	1	4	155	2	1	1	4	7	40676	20	8	160000	10	40777	40425	40550	40340	40575
160024	40304	303	1	0	1	1	10	6	528	880	72	1762	4	141	161005	10	160872	10	161168	50	1847292	1	1	0	40241	40270	40578	20152	44	20180	160367	20	160582	20	321920	40542	40461	10	1	160021	10	9	10	10	160000	10	0	2	2	1	1	2	4625	0	0	10156	3	1	1	4	130	2	1	1	5	5	40221	20	8	160000	10	40049	40040	40040	40049	40040
160024	40048	300	0	0	0	0	0	0	537	0	0	47	0	25	160011	10	160000	10	160000	50	2399027	1	1	0	40030	40049	40039	19996	3	20029	160010	20	160000	20	320000	40049	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	3	1	1	3	16	2	1	1	4	4	40036	20	7	160000	10	40040	40049	40040	40040	40040
160024	40049	300	0	0	0	0	0	0	303	0	0	340	0	25	160010	10	160000	10	160000	50	2399027	1	1	0	40021	40048	40049	19996	3	20029	160010	20	160000	20	320000	40039	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	3	1	1	4	16	2	1	1	4	3	40036	20	9	160000	10	40050	40040	40050	40040	40050
160024	40049	300	0	0	0	0	0	0	642	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	1	0	40021	40049	40048	19996	3	20019	160010	20	160000	20	320000	40049	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10024	6	2	2	4	16	4	2	2	7	6	40045	40	12	160000	10	40040	40041	40049	40040	40050
160024	40049	300	0	0	0	0	0	0	714	0	85	46	0	25	160010	10	160000	10	160000	50	2399027	0	1	0	40021	40040	40127	19996	3	20019	160010	20	160000	20	320000	40039	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	6	2	1	6	16	4	2	1	3	4	40036	40	7	160000	10	40050	40040	40050	40040	40050
160024	40049	299	0	0	0	0	0	0	471	0	17	46	0	25	160027	10	160000	10	160000	50	1320000	1	1	0	40030	40049	40039	19996	3	20029	160010	20	160000	20	320000	40052	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	3	1	1	3	16	4	2	2	7	6	40037	40	6	160000	10	40050	40040	40050	40040	40050
160024	40049	299	0	0	0	0	0	0	336	0	17	62	0	25	160011	10	160017	10	160000	50	1280000	0	1	5	40021	40040	40039	19996	3	20019	160010	20	160000	20	320000	40049	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10024	11	2	2	6	16	4	2	2	4	4	40045	40	18	160000	10	40040	40040	40040	40040	40040

UADALP (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations