Firestorm: UADALP (vector, 2S) measurements

Code:

  uadalp v0.2s, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	18	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	9	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	15	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  uadalp v0.2s, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30084	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	4	0	30	0	710	2	26	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30086	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	0	710	1	16	1	1	29634	7	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10008	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	5	0	3	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	61	29548	36	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	24	18	640	5	16	4	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	3	0	103	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	26	12	640	5	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	226	1	0	0	9	1	103	29548	25	10010	11	10016	10	10000	55	4277313	1	30018	30084	30180	28287	10	28785	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	3	640	4	16	4	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	103	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	19	3	640	4	16	5	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10038	13	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	649	5	16	5	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	5	16	5	5	29699	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	640	4	16	4	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20344	30037	30070	1	1	10021	10	9	10	10	10000	10	21	9	640	5	16	5	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10044	11	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	640	4	16	5	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	3	0	640	3	16	4	5	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  uadalp v0.2s, v0.4h

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	232	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	0	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10142	100	10000	100	10000	500	4277160	30018	30037	30037	28271	0	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	26	9	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	0	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	2	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	516	4277160	30018	30037	30037	28271	0	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	3	0	1	1	1	718	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	5799	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	0	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	4	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	0	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	4	0	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29547	25	10110	108	10000	100	10000	500	4277160	30018	30037	30037	28252	0	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	21	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	82	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uadalp v0.2s, v8.4h
  movi v1.16b, 0
  uadalp v1.2s, v8.4h
  movi v2.16b, 0
  uadalp v2.2s, v8.4h
  movi v3.16b, 0
  uadalp v3.2s, v8.4h
  movi v4.16b, 0
  uadalp v4.2s, v8.4h
  movi v5.16b, 0
  uadalp v5.2s, v8.4h
  movi v6.16b, 0
  uadalp v6.2s, v8.4h
  movi v7.16b, 0
  uadalp v7.2s, v8.4h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	151	0	553	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	284	25	80116	100	80016	100	80028	500	640196	1	20045	20147	20146	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	63	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	92	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	207	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20069	150	0	0	444	25	80010	10	80000	10	80000	50	640000	0	1	20031	20050	20050	3	22	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10027	6	2	2	4	24	4	1	2	4	4	20251	30	160000	10	20047	20051	20051	20047	20051
160024	20050	150	0	0	72	25	80010	10	80000	10	80000	50	640000	1	1	20027	20050	20046	3	22	80010	20	80133	20	160000	20046	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10030	6	2	2	4	24	4	2	2	5	5	20248	30	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	0	3793	25	80010	10	80000	10	80000	50	640000	1	1	20031	20046	20046	3	22	80010	20	80000	20	160000	20050	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	3	1	1	4	20	2	1	1	4	4	20236	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10027	3	1	1	4	20	2	1	1	4	4	20195	15	160000	10	20051	20047	20051	20051	20047
160024	20046	150	0	0	216	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	80000	20	160266	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10027	3	1	1	4	20	2	1	1	5	4	20213	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	710	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10028	3	1	1	5	20	2	1	1	4	5	20215	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	3	1	1	2	20	2	1	1	5	3	20191	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	87	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20050	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10027	3	1	1	4	20	2	1	1	4	4	20235	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	3	1	1	2	20	2	1	1	3	4	20208	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10027	3	1	1	4	20	2	1	1	3	3	20212	15	160000	10	20047	20047	20047	20047	20047

Test 5: throughput

Count: 16

Code:

  uadalp v0.2s, v16.4h
  uadalp v1.2s, v16.4h
  uadalp v2.2s, v16.4h
  uadalp v3.2s, v16.4h
  uadalp v4.2s, v16.4h
  uadalp v5.2s, v16.4h
  uadalp v6.2s, v16.4h
  uadalp v7.2s, v16.4h
  uadalp v8.2s, v16.4h
  uadalp v9.2s, v16.4h
  uadalp v10.2s, v16.4h
  uadalp v11.2s, v16.4h
  uadalp v12.2s, v16.4h
  uadalp v13.2s, v16.4h
  uadalp v14.2s, v16.4h
  uadalp v15.2s, v16.4h

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	300	0	0	0	0	17	39	25	160109	100	160008	100	160020	500	1280132	40029	40049	40039	19977	6	19991	160120	200	160032	200	320064	40040	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40049	40049	40049	40040	40040
160204	40049	300	0	0	0	0	18	31	25	160117	100	160009	100	160020	500	1320129	40021	40040	40049	19977	6	19990	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40037	0	160000	100	40040	40050	40040	40040	40050
160204	40040	300	0	0	0	0	17	30	25	160109	100	160009	100	160020	500	1280132	40020	40040	40049	19977	6	19990	160120	200	160032	200	320064	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40050	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	96	25	160117	100	160008	100	160020	500	2399131	40029	40039	40039	19977	6	19999	160120	200	160032	200	320064	40039	40040	1	1	160201	100	99	100	100	160000	100	4	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40041	40050	40049	40040
160204	40040	300	0	0	0	0	1	30	25	160109	100	160008	100	160020	500	2399159	40029	40039	40049	19977	6	19999	160120	200	160032	200	320064	40040	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40045	0	160000	100	40040	40040	40040	40050	40040
160204	40039	300	0	0	0	0	17	31	25	160108	100	160009	100	160020	500	2399159	40029	40128	40039	19977	6	19991	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40041	40050	40049
160204	40049	299	0	0	0	0	0	31	25	160108	100	160009	100	160020	500	1320129	40021	40039	40040	19977	6	20000	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40045	0	160000	100	40040	40050	40040	40041	40041
160204	40049	300	0	0	0	0	0	31	25	160117	100	160009	100	160020	500	1280132	40021	40040	40049	19977	6	19990	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	1	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40050	40050	40040
160204	40039	300	0	0	0	0	1	30	25	160117	100	160017	100	160020	500	1280132	40021	40039	40040	19977	6	19990	160120	200	160032	200	320064	40049	40114	1	1	160201	100	99	100	100	160000	100	0	45	0	1	1	1	10118	0	16	0	0	40046	0	160000	100	40040	40040	40041	40041	40040
160204	40049	300	0	0	0	0	18	64	27	160134	100	160017	100	160028	500	2387995	40038	40048	40048	19976	9	19986	160128	200	160038	200	320076	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	2	2	2	10129	1	23	1	1	40045	0	160000	100	40050	40051	40051	40058	40050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	300	0	0	0	46	25	160011	10	160000	10	160000	50	2398999	1	1	5	40020	0	40049	40049	19996	3	20029	160010	20	160000	20	320000	40039	40049	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	1	1	10	16	2	1	1	11	12	40045	15	5	160000	10	40040	40049	40040	40049	40040
160024	40049	300	0	0	17	55	25	160027	10	160001	10	160000	50	1280000	1	1	5	40020	0	40048	40048	19996	3	20028	160010	20	160000	20	320000	40049	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	11	16	2	2	2	5	11	40046	15	6	160000	10	40050	40040	40050	40050	40041
160024	40039	299	0	0	0	711	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40040	40048	19996	3	20019	160010	20	160000	20	320000	40049	40048	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	5	2	10	16	4	2	1	8	13	40045	15	5	160000	10	40041	40049	40050	40040	40050
160024	40040	300	0	0	18	62	25	160011	10	160000	10	160000	50	2399027	0	1	5	40030	0	40039	40040	19996	3	20029	160010	20	160000	20	320000	40039	40040	1	1	160021	10	9	10	10	160000	10	0	0	10024	11	5	2	10	16	4	2	2	10	11	40036	15	5	160000	10	40040	40050	40040	40050	40040
160024	40040	299	0	0	17	56	25	160011	10	160000	10	160000	50	2378910	1	1	5	40020	0	40048	40039	19996	3	20019	160010	20	160000	20	320000	40040	40049	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	12	16	2	1	1	9	12	40037	15	6	160000	10	40049	40050	40040	40049	40049
160024	40048	300	0	0	0	46	25	160011	10	160018	10	160000	50	1280000	1	1	5	40020	0	40048	40039	19996	3	20020	160010	20	160000	20	320000	40049	40049	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	12	16	2	1	1	6	14	40036	15	5	160000	10	40040	40050	40049	40049	40050
160024	40049	300	0	0	18	47	25	160027	10	160000	10	160000	50	1280000	1	1	5	40030	0	40040	40040	19996	3	20020	160010	20	160000	20	320000	40048	40048	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	10	16	2	1	1	7	12	40037	15	6	160000	10	40040	40041	40040	40050	40040
160024	40051	300	0	0	18	47	25	160011	10	160080	10	160000	50	1280000	1	1	5	40020	0	40039	40049	19996	3	20029	160010	20	160000	20	320000	40049	40039	1	1	160021	10	9	10	10	160000	10	0	3	10022	8	4	1	10	16	2	1	1	7	11	40045	15	5	160000	10	40041	40050	40040	40041	40040
160024	40040	301	0	0	0	616	25	160027	10	160017	10	160000	50	1280000	1	1	5	40020	0	40039	40049	19996	3	20020	160010	20	160000	20	320280	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	10	16	2	1	1	7	13	40036	15	6	160000	10	40050	40040	40041	40040	40041
160024	40048	299	0	0	17	56	25	160027	10	160017	10	160000	50	2399027	1	1	5	40021	0	40049	40039	19996	3	20020	160010	20	160000	20	320000	40049	40040	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	12	16	2	1	1	10	11	40046	15	5	160000	10	40040	40050	40041	40050	40040

UADALP (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations