Firestorm: UADALP (vector, 4S) measurements

Code:

  uadalp v0.4s, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	24	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	132	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	156	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	1	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	9	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	11	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  uadalp v0.4s, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30082	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10148	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	3	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	12	103	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	41	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10160	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	2	3	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	726	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  uadalp v0.4s, v0.8h

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28741	10100	200	10008	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	15	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30217
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	2	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30227
10024	30037	225	0	0	0	0	0	570	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30130	1	1	10021	10	9	10	10	10000	10	0	0	0	2	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	854	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	1	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uadalp v0.4s, v8.8h
  movi v1.16b, 0
  uadalp v1.4s, v8.8h
  movi v2.16b, 0
  uadalp v2.4s, v8.8h
  movi v3.16b, 0
  uadalp v3.4s, v8.8h
  movi v4.16b, 0
  uadalp v4.4s, v8.8h
  movi v5.16b, 0
  uadalp v5.4s, v8.8h
  movi v6.16b, 0
  uadalp v6.4s, v8.8h
  movi v7.16b, 0
  uadalp v7.4s, v8.8h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	150	0	138	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	55	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	3	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	40	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	50	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	30	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20077	150	2	2	0	66	0	57	29	80010	10	80000	10	80000	50	640000	0	1	0	20043	20060	20060	3	22	80010	20	80000	20	160000	20060	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10039	6	2	2	18	34	2	2	2	15	11	20057	40	1	160000	10	20052	20063	20063	20063	20063
160024	20060	150	0	2	0	0	0	51	27	80010	10	80000	10	80000	50	640000	1	1	5	20034	20053	20053	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	8	3	2	21	25	2	1	1	18	12	20048	20	1	160000	10	20063	20054	20054	20052	20063
160024	20051	150	1	1	0	0	0	526	29	80010	10	80000	10	80000	50	640000	1	1	5	20032	20062	20053	3	22	80010	20	80000	20	160000	20053	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10041	11	3	1	16	25	2	1	2	13	17	20059	20	1	160000	10	20052	20052	20052	20052	20054
160024	20060	150	1	1	0	225	0	933	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10038	8	3	1	17	25	12	1	1	16	17	20048	20	1	160000	10	20063	20054	20054	20052	20052
160024	20053	150	1	1	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20053	1	1	160021	10	9	10	10	160000	10	0	1	0	10038	8	3	1	16	25	2	1	1	17	16	20048	20	1	160000	10	20052	20052	20061	20052	20052
160024	20051	150	2	0	0	21	0	57	27	80010	10	80000	10	80000	50	640000	1	1	5	20034	20053	20053	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10043	11	4	1	16	34	3	2	2	17	16	20048	40	1	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	0	0	0	51	29	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	10038	8	3	2	15	34	2	1	1	17	15	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	9	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20034	20051	20053	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10041	8	4	1	13	25	2	1	1	19	19	20050	20	1	160000	10	20054	20054	20052	20052	20054
160024	20051	150	1	1	0	66	0	51	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20053	20053	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	8	4	1	20	25	1	1	1	18	18	20048	20	1	160000	10	20054	20054	20052	20052	20052
160024	20051	150	2	2	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20053	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10039	8	4	1	18	27	2	1	1	19	18	20050	20	1	160000	10	20052	20052	20052	20052	20052

Test 5: throughput

Count: 16

Code:

  uadalp v0.4s, v16.8h
  uadalp v1.4s, v16.8h
  uadalp v2.4s, v16.8h
  uadalp v3.4s, v16.8h
  uadalp v4.4s, v16.8h
  uadalp v5.4s, v16.8h
  uadalp v6.4s, v16.8h
  uadalp v7.4s, v16.8h
  uadalp v8.4s, v16.8h
  uadalp v9.4s, v16.8h
  uadalp v10.4s, v16.8h
  uadalp v11.4s, v16.8h
  uadalp v12.4s, v16.8h
  uadalp v13.4s, v16.8h
  uadalp v14.4s, v16.8h
  uadalp v15.4s, v16.8h

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40074	300	0	0	0	0	18	1	30	25	160108	100	160009	100	160020	500	2438997	1	40020	40039	40039	19977	6	19999	160120	200	160032	200	320064	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	1	16	40045	160000	100	40050	40040	40040	40050	40040
160204	40040	300	0	0	0	0	30	17	695	25	160117	100	160018	100	160020	500	1280132	1	40029	40049	40049	19977	6	20000	160120	200	160032	200	320064	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	40036	160000	100	40040	40049	40041	40041	40040
160204	40048	300	0	0	0	0	0	18	31	25	160117	100	160017	100	160020	500	2399159	0	40020	40048	40048	19977	6	19990	160120	200	160032	200	320064	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	40037	160000	100	40049	40049	40049	40049	40041
160204	40049	300	0	0	0	0	0	1	31	25	160117	100	160008	100	160020	500	1280132	0	40020	40049	40039	19977	6	19990	160120	200	160032	200	320064	40040	40049	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	40046	160000	100	40041	40050	40040	40041	40041
160204	40039	300	0	0	0	0	0	0	30	25	160117	100	160008	100	160020	500	2399131	1	40020	40049	40039	19977	6	19999	160120	200	160032	200	320064	40039	40049	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	40037	160000	100	40040	40050	40040	40041	40041
160204	40039	300	0	0	0	0	0	17	30	25	160109	100	160017	100	160020	500	2399159	0	40020	40049	40040	20036	6	19999	160120	200	160032	200	320064	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	40036	160000	100	40050	40040	40040	40050	40050
160204	40048	300	0	0	0	0	0	17	31	25	160109	100	160008	100	160020	500	1320131	0	40030	40048	40048	19977	6	20000	160120	200	160032	200	320064	40040	40049	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	40037	160000	100	40040	40040	40050	40049	40041
160204	40039	300	0	0	0	0	0	0	31	25	160109	100	160008	100	160020	500	1320129	1	40021	40039	40040	19977	6	19990	160120	200	160032	200	320064	40040	40049	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	40036	160000	100	40040	40041	40041	40040	40041
160204	40040	300	0	0	0	0	0	18	30	25	160117	100	160017	100	160020	500	2438997	1	40029	40039	40039	19977	6	19991	160120	200	160032	200	320064	40049	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	40045	160000	100	40041	40041	40041	40040	40049
160204	40039	300	0	0	0	0	27	17	39	25	160117	100	160018	100	160020	500	1280132	1	40029	40048	40049	19977	6	19991	160120	200	160032	200	320064	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	40087	160000	100	40050	40049	40041	40041	40050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	300	0	30	17	46	25	160027	10	160000	10	160000	50	1280000	1	1	5	40020	0	40039	40040	19996	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	243	0	0	10022	8	4	1	9	16	2	1	1	5	6	40045	20	9	160000	10	40040	40049	40049	40049	40040
160024	40039	300	0	0	0	46	25	160027	10	160017	10	160000	50	1280000	1	1	5	40029	0	40048	40048	20054	3	20028	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	8	16	2	1	1	8	8	40036	20	6	160000	10	40049	40040	40049	40040	40040
160024	40048	300	0	24	17	46	25	160010	10	160017	10	160152	50	1280000	1	1	5	40020	0	40048	40039	19996	3	20019	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	8	2	1	6	16	2	1	1	6	4	40036	20	9	160000	10	40040	40049	40049	40049	40049
160024	40048	300	0	0	0	46	25	160027	10	160017	10	160000	50	2398999	1	1	5	40020	0	40039	40039	19996	3	20028	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	5	16	2	1	1	9	5	40036	20	9	160000	10	40049	40040	40049	40040	40049
160024	40040	300	0	0	17	55	25	160010	10	160000	10	160000	50	2398999	1	1	5	40030	0	40040	40048	19996	3	20028	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	9	16	2	1	2	8	8	40045	20	6	160000	10	40050	40049	40040	40040	40040
160024	40039	299	0	9	17	55	25	160010	10	160001	10	160000	50	1319999	1	1	5	40029	0	40048	40039	19996	3	20019	160010	20	160000	20	320000	40049	40048	2	1	160021	10	9	10	10	160000	10	0	0	0	0	10047	8	2	1	7	16	2	1	1	6	4	40036	20	9	160000	10	40049	40040	40050	40040	40040
160024	40039	300	0	9	17	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40048	40048	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	9	16	2	1	1	7	5	40036	20	9	160000	10	40107	40049	40040	40041	40049
160024	40048	300	0	0	0	46	25	160010	10	160000	10	160000	50	2398999	1	1	5	40020	0	40048	40048	19996	3	20019	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	6	16	2	1	1	6	6	40045	20	9	160000	10	40040	40049	40040	40040	40040
160024	40039	300	0	0	17	46	25	160010	10	160000	10	160000	50	2398999	1	1	5	40020	0	40040	40048	19996	3	20019	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	6	16	2	1	1	8	8	40036	20	9	160000	10	40049	40049	40049	40040	40040
160024	40048	300	0	0	18	55	25	160027	10	160017	10	160000	50	2398999	1	1	5	40020	0	40048	40039	19996	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	1	6	16	2	1	1	5	6	40036	20	9	160000	10	40040	40049	40062	40049	40040

UADALP (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations