Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UADALP (vector, 4S)

Test 1: uops

Code:

  uadalp v0.4s, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037232406125482510001000100039831313018303730372415328951000100020003037303711100110000073216112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372201326125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230015625482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723906125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230061254825100010001000398313030183037303724153289510001000200030373037111001100011073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  uadalp v0.4s, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011613296340100001003003830038300383003830038
1020430082225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100101485004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011631296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224121032954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640341332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710160201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010123640316332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
100243003722507262954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  uadalp v0.4s, v0.8h
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000006129547251010010010000100100005004277160030018300373003728271628741101002001000820020000300373003711102011009910010010000100001117180160029646100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160030018300373003728271728741101002001000820020016300373003711102011009910010010000100001117180160029645100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160030018300373003728271628740101002001000820020016300373003711102011009910010010000100001117180160029645100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160030018300373003728271728741101002001000820020016300373003711102011009910010010000100001117170160029646100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160030018300373003728271728740101002001000820020016300373003711102011009910010010000100001117170160029646100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160130018300373003728271728740101002001000820020016300373003711102011009910010010000100001117170160029646100001003003830038300383003830038
1020430037224000006129547251010010010000100100005004277160030018300373003728271628740101002001000820020016300373003711102011009910010010000100101117170160029646100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160130018300373003728271628740101002001000820020016300373003711102011009910010010000100001117170160029646100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160030018300373003728271628740101002001000820020016300373003711102011009910010010000100001117180160029646100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160030018300373003728271728740101002001000820020016300373003711102011009910010010000100001117170160029645100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722500000156129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830217
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100002640216222962910000103003830038300383003830227
1002430037225000005706129547251001010100001010000504277160130018300373003728286328767100102010000202000030037301301110021109101010000100002640216222962910000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722500000085429547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100100640216222962910000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uadalp v0.4s, v8.8h
  movi v1.16b, 0
  uadalp v1.4s, v8.8h
  movi v2.16b, 0
  uadalp v2.4s, v8.8h
  movi v3.16b, 0
  uadalp v3.4s, v8.8h
  movi v4.16b, 0
  uadalp v4.4s, v8.8h
  movi v5.16b, 0
  uadalp v5.4s, v8.8h
  movi v6.16b, 0
  uadalp v6.4s, v8.8h
  movi v7.16b, 0
  uadalp v7.4s, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042006515001382925801161008001610080028500640196120045200652006565580128200800282001600562006520065111602011009910010016000010013011110119160200621600001002006620066200662006620066
16020420065150002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000011110119160200621600001002006620066200662006620066
16020420065150002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000011110119160200621600001002006620066200662006620066
16020420065151002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000011110119160200621600001002006620066200662006620066
16020420065150002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000011110119160200621600001002006620066200662006620066
16020420065150002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000011110119160200621600001002006620066200662006620066
160204200651510029258011610080016100800285006401961200452006520065401280128200800282001600562006520065111602011009910010016000010000011110119160200621600001002006620066200662006620066
16020420065150005025801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000011110119160200621600001002006620066200662006620066
16020420065151002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000011110119160200621600001002006620066200662006620066
160204200651500302925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000011110119160200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420077150220660572980010108000010800005064000001020043200602006032280010208000020160000200602005311160021109101016000010000100396221834222151120057401160000102005220063200632006320063
1600242006015002000512780010108000010800005064000011520034200532005332280010208000020160000200512005111160021109101016000010000100408322125211181220048201160000102006320054200542005220063
160024200511501100052629800101080000108000050640000115200322006220053322800102080000201600002005320051111600211091010160000100001004111311625212131720059201160000102005220052200522005220054
16002420060150110225093327800101080000108000050640000115200322005120051322800102080000201600002005320053111600211091010160000100001003883117251211161720048201160000102006320054200542005220052
1600242005315011000452780010108000010800005064000011520032200512005132280010208000020160000200512005311160021109101016000010010100388311625211171620048201160000102005220052200612005220052
160024200511502002105727800101080000108000050640000115200342005320053322800102080000201600002005120051111600211091010160000100001004311411634322171620048401160000102006120061200612006120061
1600242006015000000512980010108000010800005064000011520032200512005132280010208000020160000200512006011160021109101016000010000100388321534211171520048201160000102005220052200522005220052
1600242005115000090452780010108000010800005064000011520034200512005332280010208000020160000200512005111160021109101016000010000100418411325211191920050201160000102005420054200522005220054
16002420051150110660512780010108000010800005064000011520032200532005332280010208000020160000200512005111160021109101016000010000100408412025111181820048201160000102005420054200522005220052
1600242005115022000452780010108000010800005064000011520032200512005332280010208000020160000200512005111160021109101016000010000100398411827211191820050201160000102005220052200522005220052

Test 5: throughput

Count: 16

Code:

  uadalp v0.4s, v16.8h
  uadalp v1.4s, v16.8h
  uadalp v2.4s, v16.8h
  uadalp v3.4s, v16.8h
  uadalp v4.4s, v16.8h
  uadalp v5.4s, v16.8h
  uadalp v6.4s, v16.8h
  uadalp v7.4s, v16.8h
  uadalp v8.4s, v16.8h
  uadalp v9.4s, v16.8h
  uadalp v10.4s, v16.8h
  uadalp v11.4s, v16.8h
  uadalp v12.4s, v16.8h
  uadalp v13.4s, v16.8h
  uadalp v14.4s, v16.8h
  uadalp v15.4s, v16.8h
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)0918191e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440074300000018130251601081001600091001600205002438997140020400394003919977619999160120200160032200320064400404004011160201100991001001600001000011110118116400451600001004005040040400404005040040
1602044004030000003017695251601171001600181001600205001280132140029400494004919977620000160120200160032200320064400484003911160201100991001001600001000011110118016400361600001004004040049400414004140040
16020440048300000001831251601171001600171001600205002399159040020400484004819977619990160120200160032200320064400404004011160201100991001001600001000011110118016400371600001004004940049400494004940041
1602044004930000000131251601171001600081001600205001280132040020400494003919977619990160120200160032200320064400404004911160201100991001001600001000011110118016400461600001004004140050400404004140041
1602044003930000000030251601171001600081001600205002399131140020400494003919977619999160120200160032200320064400394004911160201100991001001600001000011110118016400371600001004004040050400404004140041
16020440039300000001730251601091001600171001600205002399159040020400494004020036619999160120200160032200320064400394004011160201100991001001600001000011110118016400361600001004005040040400404005040050
16020440048300000001731251601091001600081001600205001320131040030400484004819977620000160120200160032200320064400404004911160201100991001001600001000011110118016400371600001004004040040400504004940041
1602044003930000000031251601091001600081001600205001320129140021400394004019977619990160120200160032200320064400404004911160201100991001001600001000011110118016400361600001004004040041400414004040041
16020440040300000001830251601171001600171001600205002438997140029400394003919977619991160120200160032200320064400494004011160201100991001001600001000011110118016400451600001004004140041400414004040049
160204400393000000271739251601171001600181001600205001280132140029400484004919977619991160120200160032200320064400494003911160201100991001001600001000011110118016400871600001004005040049400414004140050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244003930003017462516002710160000101600005012800001154002004003940040199963200191600102016000020320000400484003911160021109101016000010024300100228419162115640045209160000104004040049400494004940040
160024400393000004625160027101600171016000050128000011540029040048400482005432002816001020160000203200004004840039111600211091010160000100000100228218162118840036206160000104004940040400494004040040
16002440048300024174625160010101600171016015250128000011540020040048400391999632001916001020160000203200004003940048111600211091010160000100000100248216162116440036209160000104004040049400494004940049
160024400483000004625160027101600171016000050239899911540020040039400391999632002816001020160000203200004004840039111600211091010160000100000100228215162119540036209160000104004940040400494004040049
1600244004030000175525160010101600001016000050239899911540030040040400481999632002816001020160000203200004003940048111600211091010160000100000100228219162128840045206160000104005040049400404004040040
1600244003929909175525160010101600011016000050131999911540029040048400391999632001916001020160000203200004004940048211600211091010160000100000100478217162116440036209160000104004940040400504004040040
1600244003930009174625160010101600001016000050128000011540020040048400481999632001916001020160000203200004003940039111600211091010160000100000100228219162117540036209160000104010740049400404004140049
160024400483000004625160010101600001016000050239899911540020040048400481999632001916001020160000203200004003940048111600211091010160000100000100228216162116640045209160000104004040049400404004040040
1600244003930000174625160010101600001016000050239899911540020040040400481999632001916001020160000203200004003940048111600211091010160000100000100228216162118840036209160000104004940049400494004040040
1600244004830000185525160027101600171016000050239899911540020040048400391999632001916001020160000203200004004840039111600211091010160000100000100228216162115640036209160000104004040049400624004940040