Firestorm: UADALP (vector, 8H) measurements

Code:

  uadalp v0.8h, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	82	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	180	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	84	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	42	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  uadalp v0.8h, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10253	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	740	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	735	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	1	0	741	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	4	0	2	0	0	640	4	16	5	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	726	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	5	16	5	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	251	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	669	5	16	5	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	1344	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	5	16	5	6	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	6	16	6	6	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	726	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	5	16	6	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	5	16	6	6	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	6	16	6	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	5	16	6	6	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	6	16	6	5	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  uadalp v0.8h, v0.16b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	16	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	16	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	66	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	16	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	16	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	16	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	16	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	16	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	16	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	16	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	16	29646	0	10000	100	30038	30038	30038	30038	30085

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	6	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	22	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	66	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	17	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uadalp v0.8h, v8.16b
  movi v1.16b, 0
  uadalp v1.8h, v8.16b
  movi v2.16b, 0
  uadalp v2.8h, v8.16b
  movi v3.16b, 0
  uadalp v3.8h, v8.16b
  movi v4.16b, 0
  uadalp v4.8h, v8.16b
  movi v5.16b, 0
  uadalp v5.8h, v8.16b
  movi v6.16b, 0
  uadalp v6.8h, v8.16b
  movi v7.16b, 0
  uadalp v7.8h, v8.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	150	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	171	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20146	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20146
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	105	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	124	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	426	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20084	150	0	0	0	0	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10034	8	1	1	10	25	2	1	2	12	10	20059	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	0	0	0	12	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20060	20062	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10036	8	2	1	10	25	2	1	1	9	10	20048	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	0	1	5	20041	20060	20060	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10035	8	4	2	12	25	2	1	1	10	11	20048	40	0	1	160000	10	20052	20052	20052	20052	20061
160024	20051	150	0	0	0	1	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	0	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10033	8	5	2	11	25	2	1	1	12	12	20048	41	0	1	160000	10	20052	20063	20052	20052	20052
160024	20051	151	0	0	0	0	0	1	0	0	710	27	80010	10	80000	10	80000	50	640000	1	1	5	20043	20060	20051	3	22	80010	20	80000	20	160000	20060	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10034	8	4	1	13	25	2	1	1	11	11	20048	40	0	1	160000	10	20061	20063	20063	20061	20063
160024	20060	150	0	0	0	0	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10033	8	4	1	12	36	4	1	2	11	12	20057	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10036	8	4	1	11	25	2	1	1	13	11	20048	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20062	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10033	8	4	1	14	36	4	1	1	9	10	20059	20	0	1	160000	10	20052	20052	20052	20052	20061
160024	20051	150	0	0	0	0	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10035	8	4	1	12	25	2	1	1	12	10	20048	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	0	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10034	8	4	1	10	25	2	1	1	11	12	20048	20	0	1	160000	10	20052	20052	20052	20052	20052

Test 5: throughput

Count: 16

Code:

  uadalp v0.8h, v16.16b
  uadalp v1.8h, v16.16b
  uadalp v2.8h, v16.16b
  uadalp v3.8h, v16.16b
  uadalp v4.8h, v16.16b
  uadalp v5.8h, v16.16b
  uadalp v6.8h, v16.16b
  uadalp v7.8h, v16.16b
  uadalp v8.8h, v16.16b
  uadalp v9.8h, v16.16b
  uadalp v10.8h, v16.16b
  uadalp v11.8h, v16.16b
  uadalp v12.8h, v16.16b
  uadalp v13.8h, v16.16b
  uadalp v14.8h, v16.16b
  uadalp v15.8h, v16.16b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	300	0	0	39	25	160108	100	160018	100	160020	500	2477133	40020	0	40049	40049	19977	6	20000	160120	200	160032	200	320064	40040	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	534	1	1	1	10118	2	16	2	2	40037	160000	100	40055	40050	40040	40049	40041
160204	40048	300	0	0	30	25	160109	100	160009	100	160020	500	1280132	40020	0	40049	40039	19977	6	20000	160120	200	160032	200	320064	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	1	16	1	1	40046	160000	100	40040	40041	40041	40040	40050
160204	40040	300	0	18	125	25	160117	100	160009	100	160020	500	1280132	40020	0	40039	40048	19977	6	19990	160120	200	160032	200	320064	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	1	16	2	2	40049	160000	100	40040	40050	40058	40050	40049
160204	40049	300	0	19	65	24	160133	100	160017	100	160028	500	2388022	40039	0	40058	40049	19976	10	19986	160128	200	160038	200	320076	40049	40058	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	6	2	2	2	10128	3	23	4	4	40045	160000	100	40050	40050	40049	40049	40050
160204	40049	300	0	17	64	26	160133	100	160035	100	160028	500	1346373	40030	0	40048	40048	19976	9	19986	160128	200	160038	200	320076	40048	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	9	2	2	2	10128	3	23	3	3	40046	160000	100	40050	40050	40050	40050	40049
160204	40049	300	0	18	64	24	160133	100	160033	100	160028	500	2388022	40030	0	40050	40049	19976	9	19988	160128	200	160038	200	320076	40049	40058	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	2	2	2	10128	3	23	3	3	40046	160000	100	40050	40049	40049	40049	40049
160204	40048	300	0	17	64	26	160117	100	160033	100	160028	500	1280598	40029	0	40048	40049	19976	9	19988	160128	200	160038	200	320076	40049	40058	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	6	2	2	2	10129	3	23	3	3	40046	160000	100	40050	40049	40049	40050	40050
160204	40049	300	0	18	446	27	160119	100	160018	100	160028	500	2388872	40030	0	40049	40049	19976	10	19986	160128	200	160038	200	320076	40049	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	93	2	2	2	10128	3	23	3	3	40046	160000	100	40050	40049	40050	40050	40072
160204	40049	300	0	17	64	24	160119	100	160033	100	160152	500	2387799	40029	0	40048	40048	19971	6	20021	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	3	2	2	2	10128	4	23	3	3	40046	160000	100	40050	40050	40059	40050	40050
160204	40048	300	0	18	89	26	160120	100	160033	100	160028	500	2387995	40032	0	40048	40049	19976	10	19989	160128	200	160038	200	320076	40049	40060	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	108	2	2	2	10128	3	23	3	4	40055	160000	100	40076	40049	40051	40050	40058

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40040	299	0	0	0	0	56	25	160010	10	160018	10	160000	50	1280000	0	1	5	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	6	6	0	10022	3	2	1	16	16	2	1	1	7	11	40036	0	40	6	0	160000	10	40040	40049	40040	40049	40049
160024	40039	300	0	0	0	17	55	25	160027	10	160017	10	160000	50	2398999	1	1	10	40020	40039	40048	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	2	8	9	0	10022	13	2	1	10	16	2	1	1	13	10	40036	0	20	6	0	160000	10	40049	40040	40040	40040	40040
160024	40048	300	0	0	0	17	55	25	160044	10	160001	10	160000	50	1319999	1	1	10	40029	40048	40039	19996	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	7	9	0	10022	13	2	1	10	16	2	1	1	12	12	40036	0	20	9	0	160000	10	40040	40049	40040	40040	40050
160024	40040	300	0	18	0	0	55	25	160011	10	160001	10	160000	50	1280000	1	1	10	40020	40039	40048	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	8	9	0	10022	13	12	1	10	16	2	1	1	8	11	40099	0	20	9	0	160000	10	40040	40049	40040	40040	40040
160024	40039	300	0	0	0	0	55	25	160044	10	160000	10	160000	50	1280000	1	1	10	40029	40039	40048	19996	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	52	3	0	10022	13	3	1	11	16	2	1	1	8	12	40036	0	20	6	0	160000	10	40049	40040	40040	40049	40050
160024	40048	300	0	0	0	17	61	25	160027	10	160000	10	160000	50	1280000	1	1	10	40020	40049	40039	19996	3	20019	160010	20	160000	20	320000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	49	6	0	10022	13	3	1	12	16	2	1	1	9	7	40045	0	20	9	0	160000	10	40050	40040	40049	40040	40041
160024	40075	300	0	0	0	0	46	25	160029	10	160000	10	160518	50	1280000	1	1	10	40020	40048	40039	19996	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	6	0	0	10022	13	3	1	7	16	2	1	1	8	10	40036	0	20	9	0	160000	10	40040	40049	40040	40040	40040
160024	40039	300	0	0	0	1	46	25	160044	10	160001	10	160000	50	2398999	1	1	10	40029	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	61	3	0	10022	13	3	1	10	16	2	1	1	10	8	40036	0	20	6	0	160000	10	40040	40049	40090	40049	40050
160024	40039	300	0	0	0	0	55	25	160011	10	160018	10	160112	50	1280000	0	0	10	40029	40048	40039	19996	3	20028	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	72	0	10022	16	4	2	12	16	4	2	1	8	10	40036	0	20	12	0	160000	10	40050	40041	40040	40040	40040
160024	40039	300	0	30	0	17	55	25	160233	10	160000	10	160000	50	2399027	1	1	10	40029	40039	40075	19996	3	20019	160010	20	160000	20	320000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	51	3	0	10022	3	1	1	12	16	2	1	1	7	10	40045	0	20	6	0	160000	10	40049	40040	40049	40040	40040

UADALP (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations