Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UADDL2 (vector, 2D)

Test 1: uops

Code:

  uaddl2 v0.2d, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000673116111787100020382038203820382038
10042037150010316872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004207315006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000373116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100012473116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uaddl2 v0.2d, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968725101001001000010010000500284768015200182003720037184223187451010020010000200200002003720037111020110099100100100001000060710511161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680152001820037200371842231874510100200100002002000020037200371110201100991001001000010000180710511161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680152001820037200371842231874510100200100002002000020037200371110201100991001001000010000210710511161119791100001002003820086200862003820038
10204200371500611968725101001001000010010000500284768015200182003720037184223187451010020010000200200002003720037111020110099100100100001000000710511161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801520018200372003718422318745101002001000020020000200372003711102011009910010010000100001860710511161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680152001820037200371842231874510100200100002002000020037200371110201100991001001000010000180710511161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768015200182003720037184223187451010020010000200200002003720037111020110099100100100001000000710501161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680152001820037200371842231874510100200100002002000020037200371110201100991001001000010000150710511161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768015200182003720037184223187451010020010000200200002003720037111020110099100100100001000090710511161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680152001820037200371842231874510100200100002002000020037200371110201100991001001000010000150710511161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000207506403163319785010000102003820038200382003820038
100242003715000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100030306403163319785010000102003820038200382003820038
100242003715000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
100242003715000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000906403163319785010000102003820038200382003820038
1002420037150000003600611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
1002420037150000000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000110006403163319785010000102003820038200382003820038
100242003715000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382008520038
100242003715000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100050006403163319785010000102003820038200382003820038
100242003715000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100020006613163319785010000102003820038200382003820038
100242003715000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100050006403163319785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uaddl2 v0.2d, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100430071011611197910100001002003820038200382003820038
102042003715000276119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000510071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100002071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500009419687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100030071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001004130071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371510061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100780640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010330640316331978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001025840640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001026150640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010630640316331978510000102003820038200382003820038
10024200371490061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uaddl2 v0.2d, v8.4s, v9.4s
  uaddl2 v1.2d, v8.4s, v9.4s
  uaddl2 v2.2d, v8.4s, v9.4s
  uaddl2 v3.2d, v8.4s, v9.4s
  uaddl2 v4.2d, v8.4s, v9.4s
  uaddl2 v5.2d, v8.4s, v9.4s
  uaddl2 v6.2d, v8.4s, v9.4s
  uaddl2 v7.2d, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015011252225801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001006035114101699200350800001002003920039200392003920039
8020420038150112472580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100200511491610102003517800001002003920039200392003920147
802042003814911247258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051141116119200350800001002003920039200392003920039
802042003815011247258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010030051141016109200350800001002003920039200392003920039
80204200381501124725801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000005114101699200350800001002003920039200392003920039
80204200381501124725801961008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000005114916910200350800001002003920039200392003920039
80204200381501124725801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000035114101699200350800001002003920039200392003920039
802042003815011247258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051141116910200350800001002003920039200392003920039
80204200381501124725801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001005300511491649200350800001002003920039200392003920039
8020420038150112472580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000511491679200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010001145020516342003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000101005020416432003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000101005020316432003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000101005020416432003580000102003920039200392003920039
80024200381500392580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001028005020316342003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100005020416342003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100035020416432003580000102003920039200392003920039
8002420038150060258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100405020416342003580000102003920039200392003920039
8002420087150039258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100005020316342003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100005020416342003580000102003920039200392003920039