Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UADDL2 (vector, 4S)

Test 1: uops

Code:

  uaddl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037160006116872510001000100026468012018203720371572318951000100020002037203711100110000073216111787100020382038203820382038
10042037150006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037170006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150006116872510001000100026468012018203720371572318951000100020002037203711100110000973116111787100020382038203820382038
10042037150006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420851500011316872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150006116872510001000100026468012018203720371572318951000100020002037203711100110001073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uaddl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000061196870251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100002071011611197910100001002003820038200382003820038
1020420037150000131196870251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000208196870251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000061196870251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000061196870251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000061196870251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003714900061196870251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000061196870251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000061196870251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000061196870251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037150961196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006402162319787010000102003820038200382003820038
1002420084150061196872510010101000010100005028488381200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037155361196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006402162319787010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006403162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uaddl2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500000611966725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000008021161119791100001002003820038200382003820038
102042003715000150611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150001440611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150003420611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284892612001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000001031968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000021506402162219785010000102003820038200382003820038
1002420037150000036001061968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200852008520038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uaddl2 v0.4s, v8.8h, v9.8h
  uaddl2 v1.4s, v8.8h, v9.8h
  uaddl2 v2.4s, v8.8h, v9.8h
  uaddl2 v3.4s, v8.8h, v9.8h
  uaddl2 v4.4s, v8.8h, v9.8h
  uaddl2 v5.4s, v8.8h, v9.8h
  uaddl2 v6.4s, v8.8h, v9.8h
  uaddl2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150000174402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051102161120035800001002003920039200392003920039
802042003815000012402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815000015402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120112800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715003639258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020316222003580000102003920039200392003920039
80024200381500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000025020116112003580000102003920039200392003920039
80024200381500039468001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020216222003580000102003920039200392003920039
80024200381500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020116222003580000102003920039200392003920039
800242003815000234258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020116112003580000102003920039200392003920039
800242003815505139258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020116112003580000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000005020116112003580000102003920039200392003920039
80024200381500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020116112003580000102003920039200392003920039
80024200381500639258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020116112003580000102003920039200392003920039
80024200381500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020116112003580000102003920039200392003920039