Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UADDLP (vector, 2D)

Test 1: uops

Code:

  uaddlp v0.2d, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716006116862510001000100026452120182037203715713189510001000100020372037111001100000373116111786100020382038203820382038
1004203715006116862510001000100026452120182037203715713189510001000100020372037111001100000673116111786100020382038203820382038
1004203715006116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715006116862510001000100026452120182037203715713189510001000100020372037111001100001073116111786100020382038203820382038
1004203715006116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004208516006116862510001000100026452120182037203715713189510001000100020372037111001100040073116111786100020382038203820382038
1004203716006116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715006116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715006116862510001000100026452120182037203715713189510001000100020372037111002100000073116111786100020382038203820382038
1004203716006116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038208520742038

Test 2: Latency 1->2

Code:

  uaddlp v0.2d, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010003071021622197910100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720084184213187451010020010000200100002003720037111020110099100100100001000484271021622197910100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010002071021622197910100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010001071021622197910100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000671021622197910100001002003820038200382003820038
102042003715001031968625101001001000010010000500284752102001820037200371842731874510256200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
1020420037150061196861031010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100036071021622197910100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010321200640216221978610000102003820038200382003820038
10024200841500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000105600640216221978610000102003820038200382003820038
10024200371500821968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715006119686451001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001034000640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000103310640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020084200371110021109101010000102000640216221978610000102003820038200382003820038
10024200371500611968625100101010036101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000104511700640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  uaddlp v0.2d, v8.4s
  uaddlp v1.2d, v8.4s
  uaddlp v2.2d, v8.4s
  uaddlp v3.2d, v8.4s
  uaddlp v4.2d, v8.4s
  uaddlp v5.2d, v8.4s
  uaddlp v6.2d, v8.4s
  uaddlp v7.2d, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420068150292580108100800081008031650064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000061115118116020085800001002003920039200392003920039
8020420038150292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
8020420038150292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
8020420038150292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
8020420038150292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
8020420038150292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001002501115118016020035800001002003920039200392003920039
8020420038150292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
8020420038150292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000101115118016020035800001002003920039200392003920039
8020420038150292580108100800081008002050064013202006820038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
8020420038150292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500012325800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020221619182003580000102003920039200392003920039
8002420038150003925800101080000108009950640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020181612232003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020171617112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020161617162003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020201618122003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020171615122003580000102003920039200392003920039
80024200381500027325800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020171619192003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020171618132003580000102003920039200392003920039
8002420038150034732580010108000010800005064000002001920038200389996310018800102080000208000020090200381180021109101080000100000502018161792003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020171616172003580000102003920039200392003920039