Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UADDLP (vector, 4S)

Test 1: uops

Code:

  uaddlp v0.4s, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371600061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371600061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371510061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  uaddlp v0.4s, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500156119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715002076119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150024299819686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150096119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150036119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000047101161119791100001002003820038200382003820038
10204200371500216119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500186119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640416661978610000102003820038200382003820038
100242003715012726196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640516561978610000102003820038200382008620038
1002420037150061196862510010101000010100005028475211200182003720037184453187671001020100002010000200372003711100211091010100001000640616561978610000102003820038200382003820038
10024200371492161196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640416551978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640616661978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640516551978610000102003820038200382003820038
10024200371500726196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640516441978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640516441978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640616651978610000102003820038200382003820038
100242003715018964196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640616661978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  uaddlp v0.4s, v8.8h
  uaddlp v1.4s, v8.8h
  uaddlp v2.4s, v8.8h
  uaddlp v3.4s, v8.8h
  uaddlp v4.4s, v8.8h
  uaddlp v5.4s, v8.8h
  uaddlp v6.4s, v8.8h
  uaddlp v7.4s, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004915000300292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013212001920038200389977699898012020080032200802312003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013202001920048200489976699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
80204200891500000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000010111511801620035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
8020420038150003420292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
802042003815000360292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004015100000004500392580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010000000050201116642003580000102003920039200392003920039
8002420038150000000000039258001010800001080000506400001200190200382003899963100188001020800002080000200382003811800211091010800001000000005020616652003580000102003920039200392003920039
8002420038150000000000039258001010800001080000506400001200190200382003899963100188001020800002080000200382003811800211091010800001000000005020516492003580000102003920039200392003920039
80024200381500000000000392580010108000010800005064000012001932003820038100133100188001020800002080000200382003811800211091010800001000000045020616492003580000102003920039200392003920039
8002420038150000000000039258001010800001080000506400001200190200382003899963100188001020800002080000200382003811800211091010800001000000005020916552003580000102003920039200392003920039
80024200381500000000000392580010108000010800005064000012001902003820038999631001880010208000020800002003820038118002110910108000010000000050201016662003580000102003920039200392003920039
80024200381500000000150039258001010800001080000506400000200190200382003899963100188001020800002080000200382003811800211091010800001000000005020416552003580000102003920039200392003920039
8002420038150000000000039258001010800001080000506400001200190200382003899963100188001020800002080000200382003811800211091010800001000000305020416542003580000102003920039200392003920039
80024200381500000000000392580010108000010800005064000012001902003820038999631001880010208000020800002003820038118002110910108000010000003050201116562003580000102003920039200392003920039
800242003815000000000005142580010108000010800005064000012001902003820038999631001880010208000020800002003820038118002110910108000010000000050206161272003580000102003920039200392003920039