Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UADDLV (vector, 8B)

Test 1: uops

Code:

  uaddlv h0, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
100430372396125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100020003037303721100110000073116112629100030383038303830383038
1004303723156125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
100430372206125472510001000100039816013018303730372414328951000100020003037303711100110000373116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037220354254725100010001000398160130183037303724143289510001000200030373037111001100001273116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100020003037303711100110000373116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  uaddlv h0, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000000263295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722400000061295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001002000071011611296330100001003003830038300383003830038
10204300372240000003837295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000000103295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000020071011613296330100001003003830038300383003830038
1020430037224000000275295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071011612296330100001003003830038300383003830038
102043003722500002640822954725101001001000010010000500427716003001830037300372826432874510100200100002002000030037300371110201100991001001000010000000710116112963325100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722400000000128295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
10024300372250000000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001040000006402162229629010000103003830038300383003830038
100243003722500000600103295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722400000000166295472510010101000010101505042771601300183003730037282863287861016120100002020000300373003711100211091010100001000000006402162329665010000103003830038300383003830038
10024300372250000000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722400000000612954725100101010000101000050427716013001830037300372828619287671001020100002020000300373003711100211091010100001000000006402162329629010000103003830038300383003830038
10024300372250000000061295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
10024300372250000000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001002000006402162229629010000103003830038300383003830038
100243003722500000000103295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001040000006402162329629010000103003830038300383003830038
10024300372250000000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162329629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  uaddlv h0, v8.8b
  uaddlv h1, v8.8b
  uaddlv h2, v8.8b
  uaddlv h3, v8.8b
  uaddlv h4, v8.8b
  uaddlv h5, v8.8b
  uaddlv h6, v8.8b
  uaddlv h7, v8.8b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150072258010810080008100800205006401321200202003920039997769990801202008003220016006420039200391180201100991001008000010000000111511816020036800001002004020040200402004020040
80204200391500220258010810080008100801205006401321200202003920039997769990801202008003220016006420039200391180201100991001008000010001200111511816020036800001002004020040200402004020040
8020420039150030258010810080008100800205006401321200202003920039997769990801202008003220016006420039200391180201100991001008000010000000111511816020036800001002004020040200402004020040
8020420039150030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000000111511816020036800001002004020040200402004020040
80204200391500139258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000000111511816020036800001002004020040200402004020040
8020420039150030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000000111511816020036800001002004020040200402004020040
8020420039150030258010810080008100800205006401321200202003920039997769990801202008003220016006420039200391180201100991001008000010000000111511816020036800001002004020040200402004020040
8020420039150030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000000111511816020036800001002004020040200402004020040
8020420039150030258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000000111511816020036800001002004020040200402004020040
8020420039150030258010810080008100800205006401321200202003920039997769990801202008003220016006420039200391180201100991001008000010000000111511816020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd2d5map dispatch bubble (d6)dadbddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500862580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000502011416406420036080000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000502005164041120036080000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000502001316006320036080000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000502001216008520036080000102004020040200402004020040
8002420039150040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000050200516007620036080000102004020040200402004020040
8002420039150082258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000050200616009520036080000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000050200416103520036080000102004020040200402004020040
80024200391500128258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000050200916005420036080000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020061600121020036080000102004020040200402004020040
8002420039150040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000050200616005420036080000102004020040200402004020040