Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UADDL (vector, 2D)

Test 1: uops

Code:

  uaddl v0.2d, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371600006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715000061168725100010001000264680120182037203715723189510001000200020372037111001100014573116111787100020382038203820382038
100420371500006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371500006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715000156116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371501006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371600006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371600006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371600006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uaddl v0.2d, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007807101161119791100001002003820038200382003820038
1020420037150002461196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007807101161119791100001002003820038200382003820038
102042003715000038491968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100012307101161119791100001002003820038200382003820038
102042003715000661196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010001507101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680200182003720037184223187451027320010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000961196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010009307101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007507101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000066196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820086200382003820085
10024200371500000611968725100101010000101000060284896302001820037200371844431876710010201000020200002003720037111002110910101000010410640216221978510000102003820038200382003820038
10024200371500000126196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150000082196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500000105196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500000105196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316221978510000102003820038200382003820038
10024200371500000536196872510010101000010100005028476800200182003720037184443187671016420100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000002521968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010330640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uaddl v0.2d, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318193f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000571196872510100100100001001000050028480540200182003720037184223187451010020010000200200002003720037111020110099100100100001001007101161119791100001002003820038200382003820038
102042003715000994196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000307101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182008620183184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000124196872510100100100001001000050028480060200182003720037184223187451010020010000200200002003720037111020110099100100100001001007101161119791100001002003820038200382003820038
102042003715000124196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000516196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000897196872510010101000010100005028476801200182003720037184443187871001020100002020000200372003711100211091010100001003640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001019105640216221978510000102003820038200382003820038
100242003715000119196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001033162640216221978510000102003820038200382003820038
100242003715000793196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150008219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000104154640216221978510000102003820038200382003820038
10024200371506061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000104869640216221978510000102003820038200382003820038
10024200371500061196872510010121000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000831196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uaddl v0.2d, v8.2s, v9.2s
  uaddl v1.2d, v8.2s, v9.2s
  uaddl v2.2d, v8.2s, v9.2s
  uaddl v3.2d, v8.2s, v9.2s
  uaddl v4.2d, v8.2s, v9.2s
  uaddl v5.2d, v8.2s, v9.2s
  uaddl v6.2d, v8.2s, v9.2s
  uaddl v7.2d, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200711510006125801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511031611200350800001002003920039200392003920039
8020420038150000103258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000005110116112003525800001002003920039200392003920039
802042003815000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010003100511011611200350800001002003920039200392003920039
802042003815000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010005403511011611200350800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680201200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
8020420038149000110625801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000100511011611200350800001002003920039200392003920039
802042003815000036525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000100511011611200350800001002003920039200392003920039
80204200381501004025801001008000010080000500640000020019200382003899733999680100200800002001601982003820038118020110099100100800001000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)0918191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004814910000051252580010108000010800006064000002001902003820038999631001880010208000020160000200382003811800211091010800001000000005020011613200350080000102003920039200392003920039
800242003815000000001042580010108000010800005064000002001902003820038999631001880010208000020160264200382003811800211091010800001000000005020011611200350880000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000000005020011611200352080000102003920039200392003920039
800242003815000000007042580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000000305020011611200350080000102003920039200392003920039
80024200381500000000602580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000010005020011623200350080000102003920039200392003920242
80024200381501000000392580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000000005020011611200350080000102003920039200392003920039
800242003815000000001232580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000000005020011611200350080000102003920039200392003920039
800242003815000000004782580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000000005022011611200350080000102003920039200392003920039
800242003815000000001252580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000000005020011611200352080000102003920039200392003920039
80024200381501000000392580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000000005020011611200350080000102003920039200392003920039