Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UADDW2 (vector, 4S)

Test 1: uops

Code:

  uaddw2 v0.4s, v0.4s, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715010316872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uaddw2 v0.4s, v0.4s, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020085200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007391161119791100001002003820038200382003820038
102042003715001031968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715007261968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000066196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162319785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006405164319785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006403163419785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006403164219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006403164319785010000102003820038200382003820038
1002420037149000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402163319785010000102003820038200382003820038
10024200371500000000103196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000200006403164419785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006403162319785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006404163319785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006403164219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uaddw2 v0.4s, v1.4s, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219858100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500124196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001002007102162219791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000157102162219791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000107102162219791100001002003820038200382003820038
10204200371500168196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101162219791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221985310000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002006520037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uaddw2 v0.4s, v8.4s, v9.8h
  uaddw2 v1.4s, v8.4s, v9.8h
  uaddw2 v2.4s, v8.4s, v9.8h
  uaddw2 v3.4s, v8.4s, v9.8h
  uaddw2 v4.4s, v8.4s, v9.8h
  uaddw2 v5.4s, v8.4s, v9.8h
  uaddw2 v6.4s, v8.4s, v9.8h
  uaddw2 v7.4s, v8.4s, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051104161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500007082580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051271161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500001032580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000000000167258001010800001080000506400000120019200382003899963100188001020800002016000020088200381180021109101080000100000000005020051416063200350080000102003920039200392003920039
8002420038150000000023925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000010300503805216062200350080000102003920039200392003920039
800242003815000000000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000046300502006216022200350080000102003920039200392003920039
8002420038150000000003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000000000502005216066200350080000102003920039200392003920039
8002420038150000000003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000000000502005616036200350080000102003920039200392003920039
80024200381500000000014825800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000000000502005616026200350080000102003920039200392003920039
8002420038150000000003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000000000502005216026200350080000102003920039200392003920039
8002420038150000000003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000000000502005616022200350080000102003920039200392003920039
8002420038150000000003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000000000502005616026200350080000102003920039200392003920039
80024200381500000000010225800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000004000502005216022200350080000102003920039200392003920039