Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UADDW (vector, 4S)

Test 1: uops

Code:

  uaddw v0.4s, v0.4s, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371601561687251000100010002646802018203720371572318951000100020002037203711100110000073216111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371504531687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150821687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
10042037150851687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uaddw v0.4s, v0.4s, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000133196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007104161119791100001002003820038200382003820038
102042003715000105196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007321161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200841500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119859100001002003820038200382003820038
10204200371500061196672510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371490061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006403162219785010000102003820038200382003820038
1002420037150072619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150016619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371502316119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100252003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100306402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uaddw v0.4s, v1.4s, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150126119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003714906119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150062319687251010010010000100100005002847680020018200372003718422718763101002001000020020000200372003711102011009910010010000100071011621198230100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715036119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371502736119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371501596119687251010010010000100100005002847680020018200372003718422918745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000046119687251001010100001010000502847680102001820037200371844431876710010201000020200002003720037111002110910101000010006400216221984510000102003820038200382003820038
10024200371610036119687251001010100001010000502847680102001820037200371844431876710010201000020200002003720037111002110910101000010006610216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680102001820037200371844431876710010201000020200002003720037111002110910101000010006400216221978510000102003820038200382003820038
10024200371500096119687251001010100001010000502847680102001820037200371844431876710010201000020200002003720037111002110910101000010006400216221978510000102003820038200382003820038
100242003715500216119687251001010100001010000502847680102001820037200371844431876710010201000020200002003720037111002110910101000010006400216221978510000102003820038200382003820038
100242003715000126119687251001010100001010000502847680102001820037200371844431884110010201000020200002003720037111002110910101000010006400216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680102001820037200371844431876710010201000020200002003720037111002110910101000010006400216221978510000102003820038200382003820038
1002420037150001746119687251001010100001010150502847680102001820037200371844431876710010201000020200002003720037111002110910101000010006400216221978510000102003820038200382003820038
100242003715000426119687251001010100001010000502847680102001820037200371844431876710010201000020200002003720037111002110910101000010006400216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680102001820037200371844431876710010201000020200002003720037111002110910101000010006400216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uaddw v0.4s, v8.4s, v9.4h
  uaddw v1.4s, v8.4s, v9.4h
  uaddw v2.4s, v8.4s, v9.4h
  uaddw v3.4s, v8.4s, v9.4h
  uaddw v4.4s, v8.4s, v9.4h
  uaddw v5.4s, v8.4s, v9.4h
  uaddw v6.4s, v8.4s, v9.4h
  uaddw v7.4s, v8.4s, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581503640258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051102161120085800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200190200382003899737999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381502440258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381502140258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500420258010010080000100800005006400001200190200382003899993999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150068258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381502440258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500039258001010800001080000506400001020019200382003899960310018800102080000201600002003820038118002110910108000010000005020007164320035080000102003920039200392003920039
8002420038150033339258001010800001080000506400001020019200382003899960310018800102080000201600002003820038118002110910108000010000005020006166420035080000102003920039200392003920039
800242003815000392580010108000010800005064000010200192003820038100300310018800102080000201600002003820038118002110910108000010220005020006166420035080000102003920039200392003920039
80024200381500939258001010800001080000506400000020019200382003899960310018800102080000201600002003820038118002110910108000010000005020006164320035080000102003920039200392003920039
800242003815000704258001010800001080000506400001020019200382003899960310018800102080000201600002003820038118002110910108000010000005020004166420035080000102003920039200392003920039
80024200381500039258001010800001080000506400001020019200382003899960310018800102080000201600002003820038118002110910108000010000005020004166420035080000102003920039200392003920039
80024200381500039258001010800001080000506400001020019200382003899960310018800102080000201600002003820038118002110910108000010000005020004166420035080000102003920039200392003920039
80024200381500039258001010800001080000506400001020019200382003899960310018800102080000201600002003820038118002110910108000010000005020004163520035080000102003920039200392003920039
8002420038150035439258001010800001080024506400001520019200382003899960310018800102080000201600002003820038118002110910108000010000005020504164620035080000102003920039200392003920039
80024200381500039258001010800001080000506400001520019200382003899960310018800102080000201600002003820038118002110910108000010000005020006164720035080000102003920039200392003920039