Firestorm: UCVTF (scalar, fixed-point, D from W) measurements

Code:

  ucvtf d0, w0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	379	3	0	361	25	2000	1000	1000	1000	1000	14075	22853	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	25	2000	1000	1000	1000	1000	14115	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	374	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	381	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf d0, w0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	3	16	3	3	129522	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	3	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	3	16	3	3	129519	10000	10000	10000	10100	130062	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119410	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	3	16	3	2	129519	10000	10000	10000	10100	130033	130034	130040	130033	130033
30204	130032	974	0	0	0	0	621	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802821	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	3	16	3	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	202	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	3	16	3	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	9	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	36	0	1310	1	3	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130056	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10064	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	177	0	1310	1	2	16	3	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130099
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	3	16	2	3	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	1008	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	1	130013	0	130032	130067	125551	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	3	16	2	3	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	1007	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125494	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	0	1270	3	16	2	3	129519	10000	0	10000	10000	10010	130033	130035	130033	130033	130036
30024	130032	1008	0	0	0	0	130017	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130019	0	130036	130087	125491	3	126262	30180	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	3	16	3	2	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	1008	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6215001	14800528	0	0	130013	0	130032	130082	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	3	3	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	1008	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214593	14801442	0	0	130013	0	130032	130116	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	3	16	3	3	129559	10000	0	10000	10000	10010	130033	130033	130033	130033	130099
30024	130032	1008	0	0	27	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125585	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	3	16	3	2	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130038
30024	130032	1008	1	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125490	20	126302	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	3	16	3	4	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130036
30024	130032	1008	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125492	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	3	16	3	2	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	1008	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130109	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	3	16	3	2	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	1008	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125512	3	126262	30010	20	10066	20000	20	10000	20000	130106	130036	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	2	3	129519	10000	0	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf d0, w8, #3
  ucvtf d1, w8, #3
  ucvtf d2, w8, #3
  ucvtf d3, w8, #3
  ucvtf d4, w8, #3
  ucvtf d5, w8, #3
  ucvtf d6, w8, #3
  ucvtf d7, w8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26712	207	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26712	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	26706	80000	80000	100	26710	26710	26710	26714	26710
160204	26709	207	0	0	12	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26713	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	1	16	0	26706	80000	80000	100	26714	26710	26710	26714	26710
160204	26709	207	0	0	0	0	26694	2	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	26706	80000	80000	100	26710	26712	26710	26710	26710
160204	26713	207	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1883318	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	26698	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26694	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	26706	80000	80000	100	26714	26710	26710	26710	26711
160204	26709	207	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1170925	1884163	26690	26715	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	1	0	1	1	1	5117	0	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26713	207	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26713	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26713	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	1	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26692	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	1	0	1	1	1	5117	0	16	0	26706	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26711	200	0	0	0	0	45	0	0	26694	3	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6814	0	60	6694	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	0	5020	3	16	0	4	2	26870	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	6	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6809	0	3	6691	160010	20	80000	80000	20	80000	80000	26709	26714	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	3	0	0	5020	2	16	0	2	2	26713	80000	80000	10	26710	26710	26717	26713	26713
160024	26713	219	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26859	26717	26727	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26713	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	0	5020	3	16	0	2	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26698	2	25	160010	10	80000	80000	10	80000	80000	50	1168880	1893093	0	0	26690	26722	26713	6690	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	0	5020	2	16	0	3	3	26706	80000	80000	10	26710	26710	26710	26710	26714
160024	26709	200	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26690	26720	26721	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	0	5020	2	16	0	2	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26825	26709	26878	6655	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	0	5020	2	16	0	2	2	26708	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26712	26772	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	0	5020	3	16	0	3	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26712	26717	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	0	5020	2	16	0	2	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26761	26711	6654	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	0	5020	2	16	0	3	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26857	26715	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	0	5020	3	16	0	4	2	26706	80000	80000	10	26710	26710	26710	26710	26710

UCVTF (scalar, fixed-point, D from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations