Firestorm: UCVTF (scalar, fixed-point, D from X) measurements

Code:

  ucvtf d0, x0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	378	377	377	377	378
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	380	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	380	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	382	377
2004	376	2	12	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	1	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	384	387	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	3	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	379	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf d0, x0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	46	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	0	0	0	0	130017	0	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130065	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20202	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	3	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	0	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130036	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130071	130064	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	0	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130147	0	130032	130032	125466	3	126248	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10056	1	4	169990	0	0	0	0	1949	1	4	318	3	2	129519	10092	10000	10000	10100	133534	132920	133572	132973	133124
30204	133594	996	0	1	38	41	5676	2552	1	133394	0	120830	658	40408	10206	20126	10074	162	24318	12009	842	6303837	15038365	1	132857	0	130032	130032	125466	248	128578	37116	248	12325	25245	256	12567	25339	133044	133639	38	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	2	130017	0	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130069	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130122	130033	130033
30204	130032	974	0	0	0	0	12	0	0	130017	1	119408	71	40129	10103	20003	10000	104	20117	10000	500	6214641	14803285	1	130013	0	130032	130032	125466	3	126242	30100	200	10000	20000	202	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	0	0	0	1905	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	133994	130828	130033
30204	130035	1008	0	0	0	0	3	0	0	130017	0	119661	109	40229	10148	20027	10006	119	21863	10784	516	6236263	14893558	1	130711	0	130032	131342	126034	94	126438	32269	208	11223	20733	200	10859	20000	131394	130035	17	1	20201	100	99	100	10100	10000	100	2	2	10006	0	2	4240	11	0	0	0	1499	1	3	68	2	4	130299	10041	10000	10000	10100	130620	131706	130847	131004	130641
30204	130922	988	0	0	0	0	0	0	0	130017	0	119408	25	40100	10100	20000	10000	100	20000	10147	500	6214497	14802709	0	130013	0	130034	130032	125466	20	126240	30100	200	10000	20000	202	10552	20000	131375	130383	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	39	0	0	130018	0	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	0	0	0	1310	1	2	16	2	2	129521	10000	10000	10000	10100	130033	130033	130038	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	0	119408	25	40100	10130	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130033	125466	3	126240	30100	200	10000	20000	200	10000	20000	130035	130034	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	114	0	0	0	0	1329	1	2	26	2	3	129520	10000	10000	10000	10100	130033	130117	130034	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	1008	0	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130068	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	4	16	2	2	129519	10003	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	1008	0	0	0	0	0	0	0	130017	119408	25	40010	10012	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	2	3	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	1008	1	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	101	126262	30010	20	10000	20130	20	10000	20000	130116	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	2	2	129525	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	1008	0	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10002	10	20000	10000	50	6214497	14800528	1	130019	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	2	3	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130034	1008	0	0	0	0	0	9	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125492	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130033	1008	0	0	0	0	0	0	0	130017	119408	25	40017	10010	20000	10000	10	20000	10000	50	6214497	14769635	1	130013	0	130032	130032	125489	3	126267	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	2	2	129521	10000	10000	10000	10010	130033	130033	130033	130377	130385
30024	131848	1027	1	1	0	27	29	3840	2200	132562	120509	677	40213	10048	20093	10062	15	23379	11519	82	6278550	14972479	1	131914	0	132721	132641	126664	158	127859	34143	26	11883	23013	22	11839	23026	132683	132646	27	1	20021	10	9	10	10010	10000	10	2	10044	1	123985	0	2043	5	412	4	8	132768	10065	10000	10000	10010	133745	133370	133784	133652	133318
30024	133271	1037	1	0	1	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	2	2	129520	10000	10000	10000	10010	130033	130069	130033	130033	130033
30024	130032	1008	0	0	0	0	0	0	0	131998	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	2	4	129561	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	1008	0	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	2	0	0	1270	2	16	2	3	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf d0, x8, #3
  ucvtf d1, x8, #3
  ucvtf d2, x8, #3
  ucvtf d3, x8, #3
  ucvtf d4, x8, #3
  ucvtf d5, x8, #3
  ucvtf d6, x8, #3
  ucvtf d7, x8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26712	207	0	0	0	0	0	0	0	0	26701	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6636	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26709	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26711	208	0	0	0	0	0	0	0	0	26704	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26713	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26714
160204	26709	207	0	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26713	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	3	0	1	1	1	5117	0	16	0	0	26710	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1883887	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26713	207	0	0	0	0	0	0	0	0	26694	2	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26692	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	206	0	0	0	0	0	0	0	0	26699	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6639	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	3	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	0	0	0	0	26709	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26710	26709	6632	0	6	6658	160134	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	0	0	0	0	26698	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1896532	26866	26714	26713	6632	0	6	6662	160135	200	80020	80020	200	80020	80024	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	206	0	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26713	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	1	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	206	0	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26714

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26709	207	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	11	16	0	3	5	26714	150	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	2	5065	5	16	0	5	3	26706	70	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	26695	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	5	16	0	5	3	26706	49	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	26697	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	3	16	0	3	5	26706	48	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	3	16	0	3	5	26706	49	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	208	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	2	0	0	0	5020	4	16	0	3	6	26706	49	80000	80000	10	26713	26710	26710	26710	26710
160024	27913	214	0	0	1	8	8	1068	704	28067	574	333	162090	10	81170	81170	10	81489	81602	61	1214698	1942075	0	0	27901	28195	28075	7191	179	152	7680	163285	20	81704	81716	20	81517	81518	28200	28083	9	1	80021	10	9	10	10	80000	10	0	0	297	81041	0	0	2	7920	2	5202	7	16	0	7	5	27833	351	80000	80000	10	27711	26722	26710	26714	26879
160024	26709	207	0	0	0	0	0	0	0	28195	622	334	162352	12	81040	81170	14	80743	81424	50	1219135	1949387	0	0	27719	28075	28204	7209	172	166	7737	163289	20	81704	81713	20	81899	81710	28209	26878	10	1	80021	10	9	10	10	80000	10	0	0	360	80260	0	1	0	7938	2	5245	5	107	0	5	5	27982	49	80000	80000	10	28205	28203	28211	28383	27545
160024	28326	218	1	0	1	5	9	1188	802	28183	647	334	162610	10	80650	81170	10	81668	81602	50	1218680	1956823	0	0	27945	28194	27040	7293	209	165	7675	162922	20	81704	81518	20	81707	81710	28378	28327	10	1	80021	10	9	10	10	80000	10	0	0	329	81301	0	0	0	7828	2	5242	7	98	0	6	4	27978	49	80000	80000	10	28202	27372	28089	28210	28211
160024	28201	219	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80130	10	80000	80534	50	1168880	1884032	0	0	27434	27545	27212	6719	162	133	7416	162557	20	81332	81431	20	81521	81329	27875	27872	9	1	80021	10	9	10	10	80000	10	4	2	224	80522	0	1	2	6098	0	5219	5	124	0	7	4	28167	50	80000	80000	10	28362	28533	28528	28693	28554

UCVTF (scalar, fixed-point, D from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations