Firestorm: UCVTF (scalar, fixed-point, H from W) measurements

Code:

  ucvtf h0, w0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	398
2004	379	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	1	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	3	73	1	16	1	1	373	1000	1000	377	383	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	384	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	374	1000	1000	377	377	377	377	377
2004	376	2	0	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	378	72	3	139	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14498	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	378	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf h0, w0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	1	0	0	1	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10049	500	6214545	14803729	1	130013	0	130032	130032	125473	6	126235	30289	200	10003	20005	200	10003	20005	130032	130033	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1317	0	2	16	3	2	129527	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	1	0	0	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125473	6	126236	30100	200	10003	20005	200	10003	20005	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1318	0	3	16	3	2	129527	10000	0	10000	10000	10100	130036	130033	130033	130033	130033
30204	130032	974	0	0	0	1	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126242	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	3	16	3	4	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130210
30204	130032	974	0	0	0	0	1	0	0	0	0	0	130023	119408	25	40117	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130034	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	3	16	3	3	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	18	0	0	0	0	1310	1	3	16	4	4	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	4	16	4	4	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	616	6214497	14805096	0	130049	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	3	16	3	4	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	3	16	3	4	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10002	0	0	0	0	0	0	0	1310	1	4	16	3	3	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	202	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	3	16	3	4	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	973	1	0	19	0	0	0	130098	119410	25	40016	10010	20000	10000	10	20000	10000	50	6214545	14800528	130013	0	130116	130032	125489	13	126345	30159	20	10000	20000	20	10062	20000	130032	130032	2	1	20021	10	9	10	10010	10000	10	2	10000	1	3	0	0	1270	1	25	1	1	129530	10000	10000	10000	10010	130033	130118	130033	130207	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	130013	0	130032	130032	125489	3	126484	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130035	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20118	10000	50	6214497	14800528	130013	0	130032	130032	125489	3	126317	30010	20	10000	20000	20	10000	20000	130032	130034	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	1	2	129519	10005	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	130013	0	130032	130032	125489	3	126305	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	3	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	2	16	1	1	129522	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130207	130035	130217	130033
30024	130116	974	0	1	1	438	104	0	130019	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10062	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	2	3	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130034	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	1	130017	119442	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130033	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	6	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130081	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	130013	0	130032	130032	125494	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	9	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130035	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	130013	0	130032	130032	125489	3	126262	30172	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf h0, w8, #3
  ucvtf h1, w8, #3
  ucvtf h2, w8, #3
  ucvtf h3, w8, #3
  ucvtf h4, w8, #3
  ucvtf h5, w8, #3
  ucvtf h6, w8, #3
  ucvtf h7, w8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26710	200	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6732	0	6	6662	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	15	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6730	0	6	6668	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	3	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	24	26694	2	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6713	0	6	6660	160135	200	80020	80024	200	80020	80020	26711	26713	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26709	80000	80000	100	26710	26713	26723	26710	26710
160204	26770	200	297	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6708	0	6	6660	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	15	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6741	0	6	6659	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	1	1	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	18	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168846	1884163	0	26690	26709	26709	6744	0	6	6669	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	3	26706	80000	80000	100	26710	26711	26710	26713	26710
160204	26717	199	9	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6734	0	6	6661	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	199	9	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6724	0	26	6663	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	18	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6714	0	6	6660	160135	200	80215	80020	200	80020	80020	26713	26729	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	18	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6703	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26711	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	0	5	16	5	5	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	15	5020	0	6	16	3	5	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	0	5	16	5	6	26712	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	149	25	160790	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6692	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	0	3	16	3	5	26706	80000	80000	10	26716	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	1	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26715	26896	6656	0	3	6700	160010	20	80000	80000	20	80026	80000	26770	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	0	3	16	5	5	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	0	3	16	5	5	26775	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	0	5	16	5	3	26717	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	0	5	16	5	7	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	0	5	16	5	5	26712	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	0	3	16	5	5	26711	80000	80000	10	26710	26710	26713	26712	26710

UCVTF (scalar, fixed-point, H from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations