Firestorm: UCVTF (scalar, fixed-point, H from X) measurements

Code:

  ucvtf h0, x0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22933	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	379	377	377	378
2004	376	2	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	377	3	364	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	2	373	1000	1000	377	377	377	377	377
2004	376	2	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	384	3	361	25	2000	1000	1000	1000	1000	14197	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	379	377	377	377
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	2	3	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf h0, x0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	0	0	0	0	0	130017	119450	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130102	130033
30204	130032	974	0	0	0	0	0	0	0	0	130017	119410	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130056	130057	130033
30204	130032	974	0	0	0	0	0	0	0	0	130017	119413	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130033	130041	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	3	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130069	130033
30204	130032	973	0	0	0	0	0	0	0	0	130017	119448	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130042	130037	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	3	2	129519	10000	10000	10000	10100	130033	130033	130049	130079	130033
30204	130032	974	0	0	0	0	0	3	0	0	130017	119441	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130116	130033	130033	130084	130033
30204	130032	974	0	1	0	0	0	0	0	0	130017	119433	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126242	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	26	5	4	129519	10000	10000	10000	10100	130033	130033	130033	130083	130033
30204	130032	974	0	0	0	0	0	0	0	0	130017	119411	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130034	130094	130063	130033
30204	130032	974	0	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130071	130033	130033	130079	130033
30204	130032	974	0	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129520	10000	10000	10000	10100	130033	130033	130033	130089	130033
30204	130032	974	0	0	0	0	0	0	0	0	130017	119427	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130072	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130035	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10006	10	20000	10000	50	6214497	14800528	0	0	130032	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130041	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	9	0	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125500	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130068	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129520	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	54	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130037	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20003	10000	10	20000	10000	50	6214497	14800528	0	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	0	1270	0	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	1	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	0	1270	1	16	1	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	3	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	8	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10002	0	0	0	0	0	0	0	1270	2	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	973	0	0	3	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	2	1	0	0	1270	1	16	1	1	129582	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf h0, x8, #3
  ucvtf h1, x8, #3
  ucvtf h2, x8, #3
  ucvtf h3, x8, #3
  ucvtf h4, x8, #3
  ucvtf h5, x8, #3
  ucvtf h6, x8, #3
  ucvtf h7, x8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80014	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80024	80024	200	80020	80020	26717	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	12	26694	0	25	160100	100	80000	80000	100	80020	80016	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80024	80020	26717	26714	1	1	80201	100	99	100	100	80000	100	80000	0	12	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1881016	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80024	80020	26795	26716	1	1	80201	100	99	100	100	80000	100	80000	0	3	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26711	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80024	200	80020	80024	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80024	80216	200	80020	80020	26709	26771	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	0	26709	26711	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26713	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26710	80000	80000	100	26714	26714	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80012	200	80020	80020	26716	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6662	160135	200	80020	80020	200	80020	80024	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80024	80024	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	0	26711	26709	6632	0	6	6658	160135	200	80400	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	954	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26710	200	0	0	26694	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	0	26690	26709	26712	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26718	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	0	5020	15	0	5	16	4	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	0	5020	3	0	4	16	2	4	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26712	26718	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	0	5020	3	0	2	16	4	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	27219	26718	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	0	5020	0	0	4	16	2	4	26706	80000	80000	10	26713	26710	26711	26710	26717
160024	26709	215	0	0	26694	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	0	5020	0	0	4	16	4	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	0	5020	0	0	4	16	4	2	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	0	5020	0	0	4	16	4	4	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	199	0	0	26694	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26711	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	0	5020	0	0	4	16	2	4	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80378	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	0	5020	0	0	4	16	4	4	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	26694	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26710	26720	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	0	5020	0	0	2	16	2	4	26706	80000	80000	10	26710	26710	26710	26710	26710

UCVTF (scalar, fixed-point, H from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations