Firestorm: UCVTF (scalar, fixed-point, S from W) measurements

Code:

  ucvtf s0, w0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	9	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	6	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	379	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	380	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	390	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	377	378	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	377	379	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf s0, w0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	1008	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	1007	0	1	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	2	1	20201	100	99	100	10100	10000	100	0	10001	0	0	0	2	1310	1	2	16	2	2	129531	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130137	1008	0	0	27	0	1	133097	120527	556	40161	10191	20111	10066	143	25008	10147	736	6271354	14979320	44	1	130013	132711	132940	126889	195	126841	31626	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	4	129546	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	1008	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	1008	0	0	0	0	0	130025	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	0	130015	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	3	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130035
30205	130032	1008	0	0	0	0	0	130020	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20202	100	99	100	10100	10000	100	0	10000	3	0	0	0	1310	1	2	16	2	2	129564	10000	10000	10000	10100	130033	130033	130036	130033	130033
30204	130032	1008	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	1008	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10049	500	6214497	14802709	0	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	4	129537	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	1007	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	2	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	3	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	1008	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	2	10016	0	0	38650	0	1310	1	2	16	3	2	129520	10002	10000	10000	10100	130033	130454	130033	130033	130795

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	18	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	973	1	0	0	1	0	0	2	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6215000	14800528	1	130013	0	130125	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	3	0	0	0	1274	16	16	15	14	129519	10000	10000	10000	10010	130033	130033	130033	130035	130033
30024	130032	974	1	0	0	1	0	0	2	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1	0	1274	14	16	12	14	129519	10000	10000	10000	10010	130125	130033	130033	130033	130033
30024	130032	974	1	0	0	1	0	0	2	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1274	13	16	10	14	129519	10000	10000	10000	10010	130033	130069	130077	130033	130033
30024	130032	974	1	0	0	1	0	78	2	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1274	14	16	14	8	129523	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	1	0	0	1	0	0	2	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	2	10000	0	0	0	0	0	0	1274	16	16	15	10	129523	10000	10000	10000	10010	130033	130033	130033	130036	130033
30024	130032	974	1	0	0	1	0	0	2	130017	119408	25	40010	10013	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1319	13	16	13	15	129521	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	1	0	0	1	0	639	2	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1274	15	16	14	9	129737	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	1	0	0	1	0	0	2	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130148	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1	1274	15	16	12	15	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	1	0	0	1	0	0	2	130017	119408	25	40010	10019	20024	10002	11	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1274	15	16	16	14	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	1	0	0	1	0	21	2	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1274	13	16	14	8	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf s0, w8, #3
  ucvtf s1, w8, #3
  ucvtf s2, w8, #3
  ucvtf s3, w8, #3
  ucvtf s4, w8, #3
  ucvtf s5, w8, #3
  ucvtf s6, w8, #3
  ucvtf s7, w8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	24	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26712	207	0	12	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	0	1	1	1	5117	2	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	26694	1	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6633	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26714	26710	26710
160204	26709	207	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6874	160136	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6636	0	6	6658	160136	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	3	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	3	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160136	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	26864	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80024	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	3	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26715	26714	26710
160204	26709	207	0	0	0	26694	3	25	160100	100	80000	80000	100	80020	80015	500	1170516	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	1	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26712	26710	26710
160204	26709	214	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26695	26709	26709	6632	0	6	6658	160136	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26712	26710	26710	26710	26710
160204	26709	207	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26712	6632	0	6	6658	160136	200	80020	80020	200	80020	80020	26710	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26710	0	80000	80000	100	26710	26710	26710	26713	26715

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26711	207	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	0	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	0	0	19	16	0	0	17	17	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	12	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	1	26690	0	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	9	5020	0	0	8	16	0	0	17	15	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	0	26709	26710	6653	0	3	6693	160010	20	80000	80000	20	80000	80000	26714	26779	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	0	0	6	16	0	0	17	8	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1886963	0	0	26690	0	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	0	0	17	16	0	0	17	17	26708	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26690	0	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26718	26718	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	0	0	12	16	0	0	6	17	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	0	26709	26709	6658	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26710	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	0	0	7	16	0	0	8	17	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	26694	2	25	160010	10	80000	80000	10	80000	80000	50	1168311	1883766	0	0	26690	0	26709	26713	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26850	1	1	80021	10	9	10	10	80000	10	80000	7	0	5020	0	0	17	16	0	0	17	17	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	0	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	0	0	6	16	0	0	17	8	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	1	26690	0	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26710	26709	1	1	80021	10	9	10	10	80000	10	80000	1	0	5020	0	0	8	34	0	0	7	14	26706	80000	80000	10	26710	26710	26710	26714	26710
160024	26709	207	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	0	26690	0	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	0	1	17	16	0	0	8	17	26706	80000	80000	10	26710	26710	26710	26710	26710

UCVTF (scalar, fixed-point, S from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations