Firestorm: UCVTF (scalar, fixed-point, S from X) measurements

Code:

  ucvtf s0, x0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	3	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	378	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	2	0	73	1	16	1	1	373	1000	1000	377	377	377	377	382
2004	376	2	0	362	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	381	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf s0, x0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130109	974	0	0	0	0	66	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	3	3	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	129520	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40137	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	3	2	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	206	10061	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	2	3	129519	10000	0	10000	10000	10100	130033	130372	130033	130033	130033
30204	130032	973	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	2	129519	10000	0	10000	10000	10100	130033	130037	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	2	2	129519	10000	0	10000	10000	10100	130033	130033	130033	130034	130033
30204	130032	975	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	2	3	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	2	16	3	2	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	9	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130035	130032	125466	3	126244	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	129519	10000	0	10000	10000	10100	130034	130033	130033	130036	130034
30204	130032	974	0	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	2	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	0	0	0	130023	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125490	3	126262	30010	20	10000	20000	20	10000	20000	130035	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	1270	6	49	4	2	129522	10000	10000	10000	10010	130381	130200	130101	130229	130033
30024	130032	974	0	0	0	0	130017	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130016	130032	130032	125490	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	16989	0	0	1270	3	16	3	3	129522	10000	10000	10000	10010	130033	130033	130092	130047	130033
30024	130032	973	0	0	0	0	130017	119484	25	40010	10010	20000	10000	10	20000	10000	50	6217110	14800528	1	130109	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130041	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	3	17	3	3	129519	10000	10000	10000	10010	130033	130033	130033	130075	130033
30024	130032	974	0	0	0	0	130017	119411	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	3	16	3	3	129519	10000	10000	10000	10010	130033	130033	130073	130062	130033
30024	130032	995	0	0	0	0	130017	119410	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	2	16	4	3	129519	10000	10000	10000	10010	130033	130033	130033	130150	130033
30024	130032	974	0	0	9	0	130017	119411	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	3	16	3	3	129519	10000	10000	10000	10010	130033	130033	130033	130101	130033
30024	130032	974	0	0	0	0	130017	119470	25	40010	10010	20009	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	3	16	3	3	129519	10000	10000	10000	10010	130033	130034	130082	130046	130033
30024	130032	974	0	0	27	0	130017	119418	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	2	16	3	3	129519	10000	10000	10000	10010	130033	130033	130033	130090	130033
30024	130032	974	0	0	0	0	130017	119415	25	40010	10010	20000	10000	10	20000	10000	50	6214545	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	3	16	3	3	129519	10000	10000	10000	10010	130075	130034	130033	130156	130033
30024	130032	974	0	0	0	0	130017	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130033	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	3	16	3	3	129519	10000	10000	10000	10010	130118	130037	130035	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf s0, x8, #3
  ucvtf s1, x8, #3
  ucvtf s2, x8, #3
  ucvtf s3, x8, #3
  ucvtf s4, x8, #3
  ucvtf s5, x8, #3
  ucvtf s6, x8, #3
  ucvtf s7, x8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	207	0	0	26702	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1886923	1	26690	26709	26709	6632	6	6658	160136	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	26706	0	80000	80000	100	26711	26712	26710	26715	26710
160204	26709	207	0	0	26697	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	26706	2	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26716	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26707	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26714
160204	26709	207	12	0	26797	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1872924	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26700	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26698	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6636	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26704	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	26706	0	80000	80000	100	26710	26710	26714	26710	26710
160204	26709	207	0	0	26710	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26710	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26716	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26713	26709	6636	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	0	26711	0	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26709	200	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	0	3	7037	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	2	16	0	1	1	26706	0	80000	80000	10	26779	26722	26715	26710	26710
160024	26709	199	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	1	16	0	1	1	26710	0	80000	80000	10	26725	26714	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26755	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	1	16	0	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	26717	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6695	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	1	16	0	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26713	200	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1169024	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26717	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	1	16	0	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26716	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	1	16	0	1	1	26706	0	80000	80000	10	26713	26718	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	1	16	0	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	1	16	0	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	16	0	0	0	5020	1	16	0	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	0	0	0	26815	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	0	5020	1	16	0	1	1	26706	0	80000	80000	10	26710	26710	26710	26710	26710

UCVTF (scalar, fixed-point, S from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations