Firestorm: UCVTF (scalar, integer, D from W) measurements

Code:

  ucvtf d0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	113	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	380	3	0	361	0	25	2000	1000	1000	1000	1000	14271	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	381	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	380	377
2004	379	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	411	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	398	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf d0, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130062	130034	130065	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129565	10000	10000	10000	10100	130069	130033	130061	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130113	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130103	130034	130108	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130080	130059	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	2	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130051	130035	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	2	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130168	130307	130119	130033	130033
30204	130032	973	0	2	7	1068	580	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130066	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	56	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130078	130035	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214545	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130076	130036	130033	130033	130033
30204	130032	973	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	9	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130099	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	2	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130142	130034	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	0	0	765	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	1	130021	0	130032	130032	125489	3	126262	30010	20	10000	20131	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130038	130033	130033	130033
30024	130032	974	0	0	0	699	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1	1270	2	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	973	0	0	0	483	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214641	14800528	0	1	130013	0	130032	130032	125489	3	126309	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	342	0	130017	119408	25	40017	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130084	130036	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	1047	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	17	0	2	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	876	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	1086	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14801996	0	1	130013	0	130032	130032	125489	3	126270	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	735	0	130017	119408	33	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130033	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	1270	1	16	0	1	1	129522	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130115	976	1	3	2	249	192	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130034	1	1	20021	10	9	10	10010	10000	10	2	10000	0	0	0	0	1270	1	16	0	1	1	129519	10000	10000	10000	10010	130033	130378	130033	130372	130033
30024	130032	974	0	0	0	129	88	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	1	130013	0	130032	130032	125489	3	126315	30010	20	10000	20000	20	10066	20000	130037	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	1270	1	16	0	1	1	129520	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf d0, w8
  ucvtf d1, w8
  ucvtf d2, w8
  ucvtf d3, w8
  ucvtf d4, w8
  ucvtf d5, w8
  ucvtf d6, w8
  ucvtf d7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch ret (8f)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26709	207	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26892	26717	1	1	80201	100	0	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	2	16	0	0	26719	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	0	26698	0	25	160100	100	80000	80000	100	80020	80015	500	1168499	1901644	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	27216	26716	1	1	80201	100	0	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	25	0	0	26717	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	3	26716	26716	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26723	26719	1	1	80201	100	0	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26714	26710	26710	26710	26710
160204	26709	207	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	0	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	1	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26713	26709	1	1	80201	100	0	99	100	100	80000	100	0	0	0	80000	0	3	1	0	0	1	1	1	5117	0	16	0	0	26714	0	80000	80000	100	26710	26813	26710	26714	26710
160204	26709	207	0	0	0	12	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26706	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	0	99	100	100	80000	100	0	0	0	80000	0	0	0	3	0	1	1	1	5117	0	16	0	0	26720	0	80000	80000	100	26710	27215	26714	26719	26710
160204	26709	207	0	0	0	0	0	26707	0	25	160100	100	80000	80000	100	80020	80015	500	1175322	1883406	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	0	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	0	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26709	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80208	80015	500	1168951	1884163	0	26690	0	26709	26709	6633	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	2	1	80201	100	0	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26715	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	0	0	26697	0	25	160100	100	80000	80000	100	80020	80013	500	1168951	1884163	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26794	26719	1	1	80201	100	0	99	100	100	80000	100	0	0	0	80000	0	0	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	d9	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26710	207	0	0	0	0	0	0	0	0	0	26702	0	25	160010	10	80000	80000	10	80000	80356	50	1168577	1884354	26690	26709	26712	6658	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	21	16	0	0	5	11	26706	0	80000	80000	10	26710	26901	27046	26843	26714
160024	26714	207	1	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26713	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	10	16	0	0	8	9	26885	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1171740	1875194	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	5	16	0	0	9	9	26959	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	7	16	0	1	7	10	26944	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	206	0	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	7	16	0	1	8	5	26896	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80570	26717	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	6	16	0	0	9	9	26904	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	7	16	0	0	5	7	26875	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1190675	1884257	26690	26709	26709	6653	0	3	6689	160010	20	80000	80378	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	7	16	0	0	7	10	26726	0	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1170391	1883845	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	5	16	0	0	4	8	26811	0	80000	80000	10	26760	26765	26717	26714	26710
160024	27209	215	2	0	1	1	7	7	810	616	0	27701	429	266	161572	10	80910	80910	10	81301	81246	50	1207649	1908018	27534	27863	27705	7097	143	127	7345	162559	20	81326	81515	20	81329	81326	27864	27915	8	1	80021	10	9	10	10	80000	10	0	0	250	80912	0	0	2	6360	4	5176	10	79	0	0	18	15	27789	0	80000	80000	10	27869	27874	27862	27878	27712

UCVTF (scalar, integer, D from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations