Firestorm: UCVTF (scalar, integer, D from X) measurements

Code:

  ucvtf d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	381	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	382	377
2004	376	2	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	380	377	378	377	377
2004	376	2	361	25	2000	1000	1000	1000	1000	14075	23107	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22951	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	380	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	362	25	2000	1000	1000	1000	1000	14227	22820	0	357	376	378	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	1	0	73	1	16	1	1	374	1000	1000	377	377	377	377	381

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf d0, x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	0	0	0	130017	119618	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126242	30100	200	10000	20000	200	10000	20000	130032	130033	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129519	10000	10000	10000	10100	130092	130037	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130072	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130158	125466	3	126242	30100	200	10000	20000	200	10000	20000	130036	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	12918	0	0	0	0	1310	1	0	2	16	2	2	129519	10000	10000	10000	10100	130033	130150	130036	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	3	2	129519	10000	10000	10000	10100	130033	130102	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129519	10000	10000	10000	10100	130033	130110	130035	130033	130033
30204	130032	973	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130034	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	2	0	162	0	0	0	0	1310	1	0	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130048	130052	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1	1310	1	0	2	16	2	2	129519	10000	10000	10000	10100	130111	130034	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130033	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	0	1329	1	0	2	33	4	2	129813	10000	10000	10000	10100	130033	130107	130083	130035	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14803054	0	130013	130032	130032	125468	3	126240	30100	200	10000	20000	200	10000	20000	130036	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	0	1310	1	0	2	16	2	2	129519	10000	10000	10000	10100	130033	130080	130068	130036	130033
30204	130032	973	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130025	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129519	10000	10000	10000	10100	130101	130038	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119411	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129519	10000	10000	10000	10100	130033	130070	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10002	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130090	130032	130034	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	130032	130033	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130035	130035	130033	130033
30024	130032	974	0	0	0	0	132627	120366	730	40190	10053	20093	10054	15	23743	11274	71	6288102	14951865	0	131984	132793	132879	126722	175	127955	35139	24	11618	24009	28	11657	23679	132789	132266	34	1	20021	10	9	10	10010	10000	10	2	2	10000	1	0	2	0	0	1852	16	345	18	16	132281	10057	10000	10000	10010	132638	133283	132908	133241	133260
30024	132974	998	0	0	6	0	130018	119408	25	40010	10014	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	2	10000	0	0	0	0	0	1270	1	16	1	2	129520	10000	10000	10000	10010	130033	130033	130083	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	2	1	129572	10000	10000	10000	10010	130036	130033	130033	130033	130033
30024	130032	973	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125494	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	2	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10066	20000	130033	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	3	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf d0, x8
  ucvtf d1, x8
  ucvtf d2, x8
  ucvtf d3, x8
  ucvtf d4, x8
  ucvtf d5, x8
  ucvtf d6, x8
  ucvtf d7, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26709	207	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80014	500	1177206	1884688	0	26690	26709	26709	6632	6	6658	160135	200	80215	80024	200	80024	80020	26730	26714	1	1	80201	100	99	100	100	80000	100	80000	0	0	3	1	1	1	5117	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26718	207	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80016	500	1168137	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80024	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	3	1	1	1	5117	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26717	207	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1169098	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	3	1	1	1	5117	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26717	207	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168983	1885529	1	26690	26710	26908	6636	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	3	1	1	1	5117	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26835
160204	26712	207	0	0	0	0	0	0	0	26694	2	25	160100	100	80000	80000	100	80020	80015	500	1166210	1875230	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	6	1	1	1	5117	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	208	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168350	1892522	1	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	9	0	27	1	1	1	5117	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26719	207	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26725	207	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	3	1	1	1	5117	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26712	210	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80014	500	1168951	1884163	0	26690	26709	26709	6632	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	3	1	1	1	5139	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26890
160204	26717	207	0	0	0	0	12	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884301	1	26690	26709	26709	6632	6	6662	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	80000	0	0	171	1	1	1	5117	16	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26711	200	0	27	0	26694	7	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26704	26715	26709	6653	3	6692	160010	20	80000	80000	20	80000	80000	26709	26715	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	5020	1	16	0	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26845	26713	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	5020	1	16	0	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	26694	0	59	160270	10	80000	80000	10	80000	80000	50	1168506	1884032	0	26854	26717	26709	6661	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	1	5020	1	16	0	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	26698	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26755	26720	26709	6658	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	5020	1	16	0	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26789	26717	26717	6658	3	6689	160010	20	80000	80000	20	80000	80000	26709	26713	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	5020	1	16	0	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26774	26715	26718	6663	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	5020	1	16	0	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26839	26720	6657	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	5020	1	16	0	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	4	24	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26838	6660	3	6689	160010	20	80000	80000	20	80189	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	5020	1	16	0	1	1	26813	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1171086	1884080	0	26838	26710	26728	6656	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	5020	1	16	0	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	200	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26825	26717	26714	6654	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	0	5020	1	16	0	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710

UCVTF (scalar, integer, D from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations