Firestorm: UCVTF (scalar, integer, H from W) measurements

Code:

  ucvtf h0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	0	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	0	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	2	2	373	0	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	0	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	111	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	1	1	373	0	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	2	2	373	0	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	382	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	0	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	0	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	2	2	373	0	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	2	16	1	1	373	0	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf h0, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	973	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130055	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6215001	14804173	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	1	0	0	0	1310	1	2	16	2	2	129520	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	1	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	36	0	0	1310	1	2	16	2	2	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119449	25	40100	10100	20000	10001	102	20118	10000	500	6214689	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	202	11045	20609	130621	130873	4	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	1310	1	3	16	2	3	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130037	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	973	0	0	0	0	0	130018	119408	32	40100	10119	20000	10000	100	20121	10000	500	6214593	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	1310	1	2	16	2	3	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	0	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	973	1	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	1310	1	2	16	3	2	129519	10000	0	10000	10000	10100	130033	130039	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	0	0	0	130017	119412	25	40010	10010	20009	10000	10	20000	10000	50	6214497	14800641	0	130013	130032	130033	125489	3	126265	30176	20	10061	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	2	16	2	1	129519	10000	10000	10000	10010	130034	130033	130065	130033	130033
30024	130032	974	1	0	9	0	130063	119408	25	40010	10013	20000	10000	10	20000	10000	50	6214497	14800528	0	130015	130032	130032	125489	3	126263	30010	20	10000	20000	20	10000	20123	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	1	16	1	2	129583	10001	10000	10000	10010	130033	130033	130197	130033	130033
30024	130032	973	0	0	9	88	130019	119408	46	40016	10010	20000	10004	10	20113	10000	60	6214497	14800528	0	130014	130119	130032	125489	3	126262	30010	20	10000	20000	20	10000	20123	130032	130078	2	1	20021	10	9	10	10010	10000	10	0	1	10000	0	1	0	0	0	1	0	1270	5	16	1	1	129519	10002	10000	10000	10010	130033	130034	130034	130034	130126
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1289	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	973	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130061	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130065	130109	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	1	16	1	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130033	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	2	16	1	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6215385	14800528	0	130013	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	973	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130013	130032	130032	125489	3	126283	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20022	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	973	0	0	0	0	130017	119408	25	40023	10010	20006	10014	10	20000	10147	50	6216534	14816402	1	130993	131189	130770	125826	39	126426	30839	20	10917	20851	20	10920	21518	130785	130082	1	1	20021	10	9	10	10010	10000	10	0	2	10009	0	1	2	4275	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130076	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf h0, w8
  ucvtf h1, w8
  ucvtf h2, w8
  ucvtf h3, w8
  ucvtf h4, w8
  ucvtf h5, w8
  ucvtf h6, w8
  ucvtf h7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	207	0	0	0	0	0	0	0	0	26704	0	25	160100	100	80000	80000	100	80020	80015	500	1169524	1885808	1	0	26690	0	26709	26720	6632	0	6	6661	160135	200	80020	80024	200	80020	80020	26709	26714	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	3	0	1	1	1	5117	0	3	16	1	2	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	1	16	2	2	26751	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	0	0	26705	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884276	1	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	3	16	2	1	26706	0	80000	80000	100	26710	26715	26710	26716	26717
160204	26709	200	0	0	0	0	0	12	0	0	26709	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	0	26694	0	26717	26723	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	2	16	1	2	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	39	0	0	26788	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26713	26709	2	1	80201	100	99	100	100	80000	100	0	0	80000	0	6	0	1	1	1	5117	0	2	16	2	2	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	0	0	26755	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26710	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	2	16	2	2	26874	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	0	0	26725	2	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5142	0	2	16	2	2	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	0	0	26716	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	2	16	2	1	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	0	0	26764	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	2	16	1	2	26706	0	80000	80000	100	26710	26713	26710	26729	26710
160204	26709	200	0	0	0	0	0	0	0	0	26706	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	0	26690	0	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	2	16	2	2	26706	0	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26709	200	0	0	0	0	26694	2	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	5	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	6	0	0	5020	5	2	0	5	16	6	4	26706	80000	80000	10	26710	26761	26798	26716	26716
160024	26709	199	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	5	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	4	0	0	0	5020	5	2	0	4	16	4	3	26706	80000	80000	10	26851	26829	26717	26726	26710
160024	26710	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	5	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	1	0	0	0	5020	5	2	0	7	16	4	4	26706	80000	80000	10	26710	26798	26821	26719	26726
160024	26709	200	0	0	0	0	26694	2	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	5	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80130	3	886	0	0	5020	5	2	0	4	16	4	6	26706	80000	80000	10	26901	26779	26716	26759	26714
160024	26709	200	0	1	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	5	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	2	0	0	0	5020	5	2	0	3	16	3	4	26706	80000	80000	10	26860	26724	26711	26713	26710
160024	26711	219	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	5	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26714	26715	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	5020	5	5	0	4	16	4	7	26706	80000	80000	10	26710	26887	26768	26788	26710
160024	26709	200	0	0	0	0	26694	2	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	5	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	0	5020	5	5	0	4	16	4	4	26706	80000	80000	10	26710	26847	26818	26721	26718
160024	26709	200	0	0	0	0	26694	2	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	5	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	3	0	0	0	5020	5	5	0	4	16	6	6	26706	80000	80000	10	26804	26888	26715	26718	26710
160024	26709	199	0	0	0	0	26694	1	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	5	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80523	0	0	0	0	5020	5	5	0	7	16	4	6	26706	80000	80000	10	26710	26710	26710	26710	26718
160024	26711	200	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	5	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	3	0	0	0	5020	5	5	0	3	16	3	4	26706	80000	80000	10	26710	26805	26831	26716	26719

UCVTF (scalar, integer, H from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations