Firestorm: UCVTF (scalar, integer, H from X) measurements

Code:

  ucvtf h0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	379	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	394	377	384	377
2004	376	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	390	378	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf h0, x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	531	130017	119408	25	40100	10100	20000	10000	125	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	17	2	2	129518	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40125	10125	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126239	30125	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	4	17	4	4	129518	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10125	20012	10000	124	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130102
30204	130032	974	0	0	0	0	130057	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	1	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130117
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14803057	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10008	125	20000	10000	626	6214554	14803008	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	127	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214593	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130035	130032	1	1	20201	100	99	100	10100	10000	100	10000	76	9	0	1312	1	4	17	4	4	129518	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10125	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130035	974	0	426	130017	119408	25	40010	10010	20004	10000	10	20000	10000	50	6215001	14804150	0	130013	0	130032	130032	125489	3	126293	30010	20	10000	20000	20	10000	20000	130036	130032	1	1	20021	10	9	4	10	10010	10000	10	10000	0	0	0	1270	3	16	1	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	0	10	10010	10000	10	10000	0	0	0	1270	3	16	1	2	129520	10000	10000	10000	10010	130074	130033	130061	130035	130033
30024	130032	974	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130036	1	1	20021	10	9	0	10	10010	10000	10	10000	0	0	0	1270	5	16	3	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	130017	119408	38	40010	10010	20000	10000	10	20000	10000	50	6215003	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	0	10	10010	10000	10	10000	0	0	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125532	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	0	10	10010	10000	10	10000	0	6	0	1270	3	16	2	2	129519	10000	10000	10000	10010	130057	130035	130036	130069	130034
30024	130032	974	0	15	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130033	1	1	20022	10	9	0	10	10010	10000	10	10000	0	0	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130014	0	130032	130032	125568	19	126273	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	0	10	10010	10000	10	10000	0	0	0	1270	4	16	2	4	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125549	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	0	10	10010	10000	10	10000	0	0	0	1270	2	16	3	4	129519	10000	10000	10000	10010	130033	130033	130033	131038	130035
30024	130035	1166	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	0	10	10010	10000	10	10000	0	0	0	1270	4	16	2	2	129577	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	33	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125511	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	0	10	10010	10000	10	10000	0	0	0	1270	4	16	2	3	129523	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf h0, x8
  ucvtf h1, x8
  ucvtf h2, x8
  ucvtf h3, x8
  ucvtf h4, x8
  ucvtf h5, x8
  ucvtf h6, x8
  ucvtf h7, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26760	26771	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	2	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80024	80020	26786	26733	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26812	26718	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80014	500	1168951	1878915	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80024	26816	26714	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	1	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	1	16	0	0	26708	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80024	26818	26715	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	16	0	0	26729	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26711	26709	6632	0	6	6658	160134	200	80020	80020	200	80020	80020	26781	26709	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80024	80020	26853	26721	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26856	26715	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80024	80020	26722	26830	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	d9	db	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26709	207	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	0	5020	4	16	0	5	4	4	26718	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	0	5020	4	16	0	5	3	3	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	1	0	0	0	0	5020	4	16	0	5	3	4	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	206	0	0	6	924	704	27541	2	25	160010	10	80000	80130	10	80000	80000	50	1168880	1884032	0	26694	26710	26709	6798	81	149	7246	161465	22	81893	80570	20	81518	80759	28200	27379	10	1	80021	10	9	10	10	80000	10	2	0	144	81303	0	0	4	4455	2	0	5020	4	16	0	5	4	4	26845	80000	80000	10	26710	26714	26714	26710	26710
160024	26709	207	1	0	5	0	616	27211	499	302	161572	10	80910	80130	10	80558	81424	50	1190824	1942530	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80189	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	2	0	254	80133	0	0	4	6990	2	0	5064	3	16	0	5	3	3	26706	80000	80000	10	26710	26710	26710	26710	28209
160024	26714	217	0	1	1	540	88	27477	432	264	160270	12	80650	80910	10	80743	81424	50	1213170	1899180	0	26690	26716	26719	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80132	1	1	0	878	0	0	5020	4	16	0	5	4	5	26706	80000	80000	10	26710	26710	26710	26764	26710
160024	26712	207	0	0	0	6	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1883256	0	26698	26715	26718	6659	0	3	6695	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	0	5020	5	16	10	0	3	4	26706	80000	80000	10	26715	26719	26716	26710	26710
160024	26713	215	0	0	0	0	0	26697	2	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	9	0	0	5020	4	16	0	0	4	4	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80026	80205	50	1182327	1892652	1	26694	26720	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26986	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	6	0	1	5020	4	16	0	0	4	4	26706	80000	80000	10	26714	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26714	26709	6653	0	3	6690	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	0	5020	3	16	0	0	5	3	26706	80000	80000	10	26710	26714	26710	26710	26710

UCVTF (scalar, integer, H from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations