Firestorm: UCVTF (scalar, integer, S from W) measurements

Code:

  ucvtf s0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	4	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	380	376	376	74	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	378	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	380	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf s0, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	1008	0	0	0	1290	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126253	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	1	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	9	0	0	0	1310	1	2	16	3	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	0	0	130017	119419	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130069	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	1310	1	2	16	3	2	129519	10000	10000	10000	10100	130033	130033	130035	130035	130033
30204	130032	999	0	0	0	0	2992	1	133365	120936	875	40423	10217	20123	10082	159	24779	11960	833	6320753	15034491	0	132619	0	132979	133389	126882	247	128030	36655	266	12144	24986	246	12514	24872	132952	133412	37	1	20201	100	99	100	10100	10000	100	2	10058	0	0	2	175878	0	0	0	2068	1	4	390	5	2	132199	10000	10000	10000	10100	132442	132658	132583	132781	132109
30204	132716	1027	1	47	33	7071	3960	1	132026	120299	496	40282	10182	20087	10048	146	23031	11372	500	6214497	14802709	0	132077	0	132398	131023	125466	3	126464	36388	233	11884	23540	234	11511	23498	132190	132756	31	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	3	0	0	0	1310	1	2	16	2	1	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	1092	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130033	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1	0	1310	1	2	16	2	1	129522	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	1008	0	0	0	549	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	105	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6215203	14802709	0	130013	0	130032	130032	125513	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130038
30204	130032	974	0	0	0	840	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	1310	1	2	16	1	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	991	0	0	0	258	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	0	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130034	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130033	130033	130038	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214593	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	2	3	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130132	130034	130035	130974
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	132401	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	2	3	129519	10000	10000	10000	10010	130034	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30179	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	2	2	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	0	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	2	3	129519	10000	10000	10000	10010	130033	130035	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf s0, w8
  ucvtf s1, w8
  ucvtf s2, w8
  ucvtf s3, w8
  ucvtf s4, w8
  ucvtf s5, w8
  ucvtf s6, w8
  ucvtf s7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	200	0	0	0	0	0	0	0	0	26761	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	1	16	0	0	26706	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	0	0	26699	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6640	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26782	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26893	215	1	0	1	1	9	9	924	704	28519	720	25	160622	106	81479	81560	108	82055	82136	533	1250428	1977546	0	28370	29025	29282	7260	318	263	8523	165562	206	82881	82117	210	81356	80023	28215	28633	12	1	80201	100	99	100	100	80000	100	0	4	582	81950	0	0	13890	0	2	2	2	5127	1	24	1	1	26707	1	80000	80000	100	26713	26711	26716	26712	26715
160204	26710	207	0	0	0	0	3	3	9	0	26695	725	331	162444	102	81170	81430	100	81512	81975	522	1237382	1912621	0	27526	28033	28695	7118	41	197	7626	164884	202	81924	81929	204	81934	80596	28364	28047	15	1	80201	100	99	100	100	80000	100	0	0	504	81430	0	0	14170	0	1	1	1	5318	3	170	2	2	28444	3	80000	80000	100	26711	26720	26711	26711	26711
160204	26710	208	0	0	0	0	0	0	0	0	28226	904	402	163485	103	81560	82210	110	82240	82670	527	1256629	1996592	0	28414	29185	29366	7654	357	322	8276	164883	206	82004	83239	206	83234	83234	29204	29659	19	1	80201	100	99	100	100	80000	100	0	2	623	81300	0	0	14015	0	1	1	1	5117	0	16	0	0	26779	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	1	0	1	13	13	1716	1144	29013	1012	542	164267	104	81690	81950	110	82599	82670	533	1248924	1984758	0	28643	28929	29205	7139	453	318	7969	165251	210	82884	83452	206	82313	83441	28748	29585	12	1	80201	100	99	100	100	80000	100	0	0	35	80000	0	0	0	0	2	2	2	5128	1	24	1	1	26761	0	80000	80000	100	26712	26712	26713	26711	26711
160204	26710	214	0	0	0	0	0	0	0	0	26697	0	25	160100	100	80000	80000	100	80023	80018	500	1168352	1884637	0	26691	26710	26710	6621	0	10	6645	160141	200	80023	80023	200	80023	80023	26710	26710	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	2	2	1	5117	0	16	0	1	26870	0	80000	80000	100	26710	26710	26710	26710	26856
160204	26710	229	0	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26798	0	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26715	0	80000	80000	100	26710	26710	26710	26712	26710
160204	26709	200	0	0	0	0	0	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26690	26709	26709	6632	0	6	6658	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26805	0	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	a9	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26709	200	0	0	26694	2	25	160010	10	80000	80000	10	80000	80000	50	1168389	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	4	16	2	4	26706	80000	80000	10	26712	26719	26711	26719	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26713	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	2	16	4	2	26706	80000	80000	10	26716	26710	26712	26710	26710
160024	26709	200	0	48	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1170084	1884032	1	26694	27043	26712	6661	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	4	16	2	4	26709	80000	80000	10	26718	26714	26718	26714	26710
160024	26711	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	4	16	2	4	26706	80000	80000	10	26715	26710	26712	26710	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26711	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	4	16	4	2	26706	80000	80000	10	26716	26718	26710	26727	26710
160024	26709	200	0	0	26694	3	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	6	16	4	2	26706	80000	80000	10	26716	26718	26711	26715	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	2	16	4	4	26706	80000	80000	10	26716	26719	26710	26723	26710
160024	26709	200	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	2	16	4	2	26706	80000	80000	10	26713	27215	26717	26715	26710
160024	26712	200	0	0	26694	5	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26695	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	2	16	4	4	26706	80000	80000	10	26719	26714	26720	26710	26710
160024	26709	200	0	0	26694	26	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	0	5020	0	4	16	2	4	26706	80000	80000	10	26711	26718	26710	26710	26710

UCVTF (scalar, integer, S from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations