Firestorm: UCVTF (scalar, integer, S from X) measurements

Code:

  ucvtf s0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	376	3	0	0	361	0	25	2000	1000	1000	1000	1000	14132	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	2	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	73	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	1	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	2	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	377	377	377	377	377
2004	376	3	0	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	357	376	376	72	3	109	2000	1000	1000	1000	1000	376	376	1	1	1001	1000	1000	0	0	73	1	16	1	1	376	1000	1000	377	377	377	377	377

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf s0, x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130073	130068	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	973	0	0	0	0	130017	119456	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	973	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	0	130032	130032	125466	3	126240	30100	200	10000	20131	200	10000	20000	130035	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10002	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130074	130038	130034	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	3	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130033	130034	130033	130038	130033
30205	130058	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	6	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130035	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214497	14802709	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20128	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	1	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20003	10000	100	20000	10000	500	6214497	14802709	130013	0	130032	130035	125496	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	129519	10000	10000	10000	10100	130071	130034	130033	130033	130033
30204	130032	974	0	0	0	0	130017	119408	25	40100	10100	20004	10000	100	20000	10000	500	6214497	14802709	130013	0	130032	130032	125466	3	126240	30100	200	10000	20000	200	10000	20000	130032	130032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	1	0	1310	1	1	16	2	2	129519	10000	10000	10000	10100	130033	130033	130033	130033	130033

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130077	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	3	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	21	0	130017	119409	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130034
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130013	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	7	0	0	130192	119409	25	40010	10010	20000	10006	10	20118	10049	50	6214497	14800528	1	130062	0	130032	130032	125491	3	126263	30010	20	10120	20000	20	10000	20000	130034	130033	1	1	20021	10	9	10	10010	10000	10	0	10000	0	3	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130368	130033	130036	130036	130035
30024	130032	974	0	0	27	0	130018	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130018	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	0	3	129519	10000	10000	10000	10010	130033	130049	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	0	130042	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130036	130035	130034	130033	130033
30024	130034	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130093	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130519	130034	130033	130291	130033
30024	130032	977	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130074	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20000	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	4	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033
30024	130032	974	0	0	0	0	130017	119408	25	40010	10010	20000	10000	10	20000	10000	50	6214497	14800528	1	130092	0	130032	130032	125489	3	126262	30010	20	10000	20000	20	10000	20131	130032	130032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	129519	10000	10000	10000	10010	130033	130033	130033	130033	130033

Test 3: throughput

Count: 8

Code:

  ucvtf s0, x8
  ucvtf s1, x8
  ucvtf s2, x8
  ucvtf s3, x8
  ucvtf s4, x8
  ucvtf s5, x8
  ucvtf s6, x8
  ucvtf s7, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26709	207	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	6	6842	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	1	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26714
160204	26709	206	1	1	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26691	26709	26709	6632	6	6831	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	26695	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	6	6785	160135	200	80020	80020	200	80020	80020	26713	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	6	6800	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26713	80000	80000	100	26714	26710	26710	26710	26710
160204	26713	207	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	6	6812	160136	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	9	26699	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26694	26709	26709	6632	6	6822	160134	200	80020	80020	200	80020	80020	26714	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5183	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26709	6632	6	6751	160135	200	80020	80020	200	80020	80020	26709	26710	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	26694	2	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26713	26713	6632	6	6778	160134	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26714	26710	26710	26710	26710
160204	26713	207	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26690	26709	26713	6632	6	6755	160135	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	207	0	0	0	26694	0	25	160100	100	80000	80000	100	80020	80014	500	1168951	1884163	26690	26709	26709	6632	6	6818	160136	200	80020	80020	200	80020	80020	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26710	26710	26710	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26710	207	0	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168628	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	12	0	0	26709	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26700	26715	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	3	0	0	5219	1	115	2	1	28074	80000	80000	10	28531	28588	28549	28547	28533
160024	28080	220	0	0	0	0	12	12	1332	616	1	28532	782	403	163130	10	81430	81329	10	81116	81958	50	1229847	1963137	0	28373	28369	28533	7416	256	208	7887	164012	20	82280	82286	20	82280	81140	28699	28586	12	1	80021	10	9	10	10	80000	10	0	0	403	81562	0	0	9635	2	0	5284	1	124	1	1	28431	80000	80000	10	28690	28202	28693	28694	29202
160024	28541	224	0	0	1	1	5	12	1455	528	0	28192	0	25	160010	10	80000	80000	10	80000	80000	50	1168410	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	292	81170	0	0	5308	0	0	5154	2	79	2	1	27692	80000	80000	10	28200	28199	28202	28045	28092
160024	28035	218	1	1	0	1	5	8	1191	792	0	28211	652	401	162350	12	81170	81300	10	81671	81602	50	1219117	1942361	0	27809	28039	27706	7181	48	3	6689	160010	20	80000	80000	20	80000	80000	26709	26812	1	1	80021	10	9	10	10	80000	10	0	0	37	80132	0	0	3	0	0	5196	2	70	1	1	27968	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	1	0	0	0	7	5	531	704	0	27904	146	231	160532	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	38	113	6690	160373	20	80000	80000	20	80189	80192	27040	26883	1	1	80021	10	9	10	10	80000	10	4	4	74	80910	0	4	3505	2	0	5020	1	16	1	1	26706	80000	80000	10	27713	26710	26710	26880	26713
160024	27047	210	1	0	0	0	4	9	264	968	0	28032	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26714	26713	6653	0	3	6692	160010	20	81707	80756	20	80189	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	2	2	229	80000	0	0	0	0	0	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	18	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	1	34	1	1	26727	80000	80000	10	26710	26710	26710	26710	26710
160024	26709	207	0	0	0	0	0	0	0	0	0	26694	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26690	26709	26709	6653	0	3	6689	160010	20	80000	80000	20	80000	80000	26709	26709	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	0	0	5020	1	16	1	1	26706	80000	80000	10	26710	26710	26710	26710	26710

UCVTF (scalar, integer, S from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations