Firestorm: UDOT (by element, 8B) measurements

Code:

  udot v0.2s, v1.8b, v2.4b[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  udot v0.2s, v1.8b, v2.4b[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	213	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	2	16	1	1	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	217	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	1	16	1	1	29647	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	149	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30086	30038
10204	30037	233	24	0	103	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	3	0	0	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	128	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28762	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	112	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	0	0	0	0	710	1	4	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	1	188	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	1	149	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	3	16	3	3	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	233	0	0	0	61	29548	25	10010	10	10000	0	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	61	29548	25	10010	10	10000	0	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	75	29548	25	10010	10	10000	0	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	12	0	61	29548	25	10010	10	10000	0	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	726	29548	25	10010	10	10000	0	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	3	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	61	29548	25	10010	10	10000	0	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	89	29548	25	10010	10	10000	0	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	61	29548	25	10010	10	10000	0	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	61	29548	25	10010	10	10000	0	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	89	29548	25	10010	10	10000	0	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  udot v0.2s, v0.8b, v1.4b[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	85	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	170	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	845	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	5	0	0	0	710	0	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	1	3	0	254	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	124	29548	25	10100	100	10000	103	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	710	0	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	187	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	2823	0	710	0	1	16	1	1	29634	10000	100	30078	30038	30038	30038	30038
10204	30037	233	0	0	0	12	103	29548	65	10143	100	10000	100	10000	557	4285455	1	30198	30085	30179	28265	17	28817	10567	210	10000	220	31989	30277	30278	5	1	10201	100	99	100	100	10000	100	0	2	0	1	0	8290	0	710	0	3	32	1	1	29634	10000	100	30038	30136	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	232	0	0	0	0	883	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	0	10	10000	10	0	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	103	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	0	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	0	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	0	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	128	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	0	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	168	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	0	10	10000	10	0	3	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	84	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	2	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	0	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	147	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	0	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	0	124	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	0	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  udot v0.2s, v1.8b, v0.4b[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	0	219	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	474	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28818	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	6	2	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	474	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	45	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	465	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29702	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	396	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	417	0	0	726	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10013	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	0	16	0	0	29647	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	99	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28272	6	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	0	16	0	0	29647	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	120	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	233	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	3	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	103	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  udot v0.2s, v8.8b, v9.4b[1]
  movi v1.16b, 0
  udot v1.2s, v8.8b, v9.4b[1]
  movi v2.16b, 0
  udot v2.2s, v8.8b, v9.4b[1]
  movi v3.16b, 0
  udot v3.2s, v8.8b, v9.4b[1]
  movi v4.16b, 0
  udot v4.2s, v8.8b, v9.4b[1]
  movi v5.16b, 0
  udot v5.2s, v8.8b, v9.4b[1]
  movi v6.16b, 0
  udot v6.2s, v8.8b, v9.4b[1]
  movi v7.16b, 0
  udot v7.2s, v8.8b, v9.4b[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20092	155	2	0	2	0	21	0	4	59	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	1	0	0	10126	14	16	13	14	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	156	3	0	3	0	3	0	4	65	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10128	14	16	12	15	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	155	3	0	3	0	0	0	4	65	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	3	10128	15	16	12	14	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	156	3	0	3	0	0	0	4	65	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10125	11	16	15	13	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	155	5	0	5	0	0	0	4	338	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10127	14	16	14	14	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	156	3	0	3	0	0	0	4	83	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10127	13	16	14	12	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	155	2	0	3	0	0	0	4	65	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10127	14	16	13	13	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	156	3	0	3	0	24	0	3	59	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10126	6	16	14	15	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	155	2	0	3	0	6	0	3	760	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10124	11	16	10	12	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	155	3	0	3	0	39	0	4	59	25	80100	100	80000	100	80104	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10127	16	16	14	15	20061	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c3	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20142	155	0	2	2	27	0	63	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	20060	20261	3	22	80012	20	80000	20	240000	20061	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10040	11	3	2	21	34	4	1	2	14	13	20048	2	20	2	160000	10	20061	20128	20072	20063	20061
160024	20051	155	0	1	2	0	0	51	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20249	3	22	80012	20	80000	20	240000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10042	11	4	1	16	25	2	2	1	8	14	20058	2	40	2	160000	10	20052	20061	20052	20061	20052
160024	20051	155	0	1	2	255	0	51	30	80012	12	80000	12	80000	62	640000	1	1	5	20041	20060	20226	11	44	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10037	8	5	2	14	25	4	2	2	13	15	20057	2	40	1	160000	10	20061	20061	20061	20052	20061
160024	20060	155	0	0	0	0	0	63	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	20051	20209	3	22	80012	20	80000	20	240000	20060	20051	1	1	160021	10	9	10	10	160000	10	0	0	3	0	0	10041	11	6	2	8	34	4	2	2	16	16	20048	2	40	3	160000	10	20052	20052	20061	20052	20061
160024	20060	156	0	1	1	0	0	51	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	20051	20188	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10037	16	6	1	16	34	2	2	1	14	18	20058	2	40	1	160000	10	20052	20052	20052	20052	20052
160024	20051	155	0	1	1	51	0	438	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20202	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10038	13	6	1	14	25	2	1	1	9	16	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	155	0	1	2	15	1	97	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20192	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10036	13	7	1	13	34	2	1	1	14	14	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	156	0	0	1	15	0	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20189	24	22	80117	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10036	13	7	2	16	25	2	1	1	12	12	20048	2	20	1	160000	10	20052	20143	20052	20052	20052
160024	20051	155	0	1	0	6	0	51	31	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20164	3	22	80012	20	80000	20	240000	20061	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10038	13	6	1	14	25	2	2	1	13	14	20057	2	20	1	160000	10	20052	20052	20052	20052	20053
160024	20051	156	0	1	1	348	0	85	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20060	20163	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10037	13	7	1	13	25	2	1	1	13	13	20048	2	20	1	160000	10	20061	20061	20061	20052	20052

Test 6: throughput

Count: 16

Code:

  udot v0.2s, v16.8b, v17.4b[1]
  udot v1.2s, v16.8b, v17.4b[1]
  udot v2.2s, v16.8b, v17.4b[1]
  udot v3.2s, v16.8b, v17.4b[1]
  udot v4.2s, v16.8b, v17.4b[1]
  udot v5.2s, v16.8b, v17.4b[1]
  udot v6.2s, v16.8b, v17.4b[1]
  udot v7.2s, v16.8b, v17.4b[1]
  udot v8.2s, v16.8b, v17.4b[1]
  udot v9.2s, v16.8b, v17.4b[1]
  udot v10.2s, v16.8b, v17.4b[1]
  udot v11.2s, v16.8b, v17.4b[1]
  udot v12.2s, v16.8b, v17.4b[1]
  udot v13.2s, v16.8b, v17.4b[1]
  udot v14.2s, v16.8b, v17.4b[1]
  udot v15.2s, v16.8b, v17.4b[1]

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40072	301	0	0	17	41	25	160100	100	160018	100	160000	500	1280000	0	40020	0	40039	40039	19973	3	19997	160100	200	160000	200	480000	40048	40048	2	1	160201	100	99	100	100	160000	100	0	0	10110	0	1	16	1	1	40046	160000	100	40049	40049	40049	40040	40040
160204	40048	300	0	0	0	41	25	160100	100	160000	100	160000	500	2438865	0	40020	0	40039	40049	19973	3	19997	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	10110	0	1	16	1	1	40045	160000	100	40040	40040	40040	40050	40049
160204	40048	300	0	0	0	41	25	160101	100	160000	100	160000	500	1280000	1	40030	0	40039	40039	19973	3	20006	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	10110	0	1	16	1	1	40036	160000	100	40040	40049	40040	40040	40041
160204	40049	299	0	0	0	50	25	160117	100	160017	100	160000	500	2398999	1	40029	0	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	10110	0	1	16	1	1	40036	160000	100	40050	40040	40040	40040	40040
160204	40039	300	0	0	0	41	25	160100	100	160000	100	160000	500	1280000	0	40030	0	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	10110	0	1	16	1	1	40046	160000	100	40040	40041	40049	40040	40040
160204	40048	300	0	0	17	46	25	160100	100	160017	100	160000	500	1280000	1	40020	0	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	10110	0	1	16	1	1	40036	160000	100	40050	40040	40040	40041	40041
160204	40039	300	0	0	0	41	25	160100	100	160000	100	160000	500	2398999	0	40020	0	40039	40039	19973	3	20006	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	3	10110	0	1	16	1	1	40045	160000	100	40040	40040	40049	40040	40049
160204	40040	300	0	0	0	41	25	160100	100	160000	100	160000	500	1280000	0	40020	0	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	10110	0	1	16	1	1	40045	160000	100	40040	40040	40040	40049	40040
160204	40039	300	0	0	0	41	25	160100	100	160017	100	160000	500	1280000	0	40020	0	40048	40048	19973	3	20006	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	36	10110	0	1	16	1	1	40045	160000	100	40041	40049	40040	40040	40049
160204	40039	300	0	0	1	41	25	160117	100	160000	100	160000	500	1280000	0	40020	0	40039	40039	19973	3	20006	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	10110	0	1	17	1	1	40045	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40048	310	0	0	0	0	0	0	0	0	0	0	52	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40048	40039	19996	3	20028	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	11	5	2	10	16	4	2	2	2	4	40036	0	40	12	160000	10	40040	40049	40049	40049	40040
160024	40039	310	0	0	0	0	0	0	0	0	0	0	53	0	25	160027	10	160000	10	160000	50	1280000	0	1	5	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	5	2	2	16	2	2	2	6	4	40036	0	20	18	160000	10	40049	40040	40040	40040	40049
160024	40039	310	0	0	0	0	0	0	0	0	17	0	935	0	25	160010	10	160001	10	160000	50	2398999	0	1	5	40030	40048	40039	19996	3	20019	160010	20	160000	20	480000	40049	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	4	2	2	16	4	1	2	4	6	40036	0	20	12	160000	10	40040	40040	40040	40049	40049
160024	40039	310	0	0	0	0	0	0	0	0	0	0	46	0	25	160027	10	160000	10	160000	50	1280000	0	1	5	40029	40049	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	5	1	4	16	2	1	1	2	4	40036	0	40	6	160000	10	40040	40040	40040	40040	40106
160024	40039	310	0	0	0	0	0	0	0	0	17	0	46	0	25	160027	10	160018	10	160000	50	2398999	1	1	5	40020	40049	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	4	2	8	16	2	1	1	2	4	40036	0	20	6	160000	10	40040	40040	40040	40041	40040
160024	40039	311	0	0	0	0	0	0	0	0	0	0	6054	0	25	160010	10	160000	10	160000	50	2398999	1	1	5	40020	40049	40039	19996	3	20020	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	5	2	4	16	2	2	1	2	4	40036	0	20	6	160000	10	40040	40050	40040	40040	40040
160024	40039	310	0	0	0	0	0	0	0	0	0	0	46	0	25	160010	10	160017	10	160000	50	1280000	1	1	5	40020	40048	40048	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	11	4	1	4	16	2	1	1	2	4	40036	0	20	12	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	0	0	0	0	9	0	0	0	52	0	25	160010	10	160000	10	160000	50	1319997	1	1	5	40020	40048	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160022	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	4	1	2	16	2	1	1	4	2	40036	0	20	6	160000	10	40041	40040	40049	40049	40049
160024	40039	310	0	0	0	0	0	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	3	20019	160165	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	4	2	4	16	4	1	1	9	7	40036	0	21	6	160000	10	40040	40040	40040	40040	40040
160024	40039	311	0	0	0	0	0	0	0	0	0	0	46	0	25	160027	10	160000	10	160000	50	1280000	1	1	5	40243	40048	40048	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	4	1	4	16	2	1	1	6	5	40036	0	20	6	160000	10	40040	40040	40040	40040	40040

UDOT (by element, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations