Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UDOT (vector, 16B)

Test 1: uops

Code:

  udot v0.4s, v1.16b, v2.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230000900612548251000100010003983130301830373037241532895100010003000303730371110011000000000073116112630100030383038303830383038
10043037240000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073116112630100030383038303830383038
100430372400000001242548251000100010003983131301830373037241532895100010003000303730371110011000000000073116112630100030383038303830383038
10043037240000000612548251000100010003983130301830373037241532895100010003000303730371110011000000100073116112630100030383038303830383038
10043037240000000612548251000100010003983130301830373037241532895100010003000303730371110011000000000073116112630100030383038303830383038
10043037240000000612548251000100010003983130301830373037241532895100010003000303730371110011000000000073116112630100030383038303830383038
10043037230000000612548251000100010003983130301830373037241532895100010003000303730371110011000000000073116112630100030383038303830383038
100430372400001200612548251000100010003983130301830373037241532895100010003000303730371110011000000000073116112630100030383038303830383038
10043037240000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073116112630100030383038303830383038
100430372300000001032548251000100010003983131301830373037241532895100010003000303730371110011000000000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  udot v0.4s, v1.16b, v2.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037232930612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071204163329634100001003003830038300383003830038
1020430037233270612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071004163329634100001003003830038300383003830038
1020430037232270612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071003163329634100001003003830038300383003830038
10204300372410027982954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000371003163329634100001003003830038300383003830038
10204300372321740612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071003163329634100001003003830038300383003830038
1020430037233120612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071003163329634100001003003830038300383003830038
1020430037233240612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071003163329634100001003003830038300383003830038
1020430037232150612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071203163329634100001003003830038300383003830038
10204300372333001032954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000371003163329634100001003003830038300383003830038
10204300372321680822954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010001071003163329634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037233006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100640316222963010000103003830038300383003830038
1002430037233006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100640216322963010000103003830038300383003830038
10024300372460014729548251001010100071010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225008229548251001010100001010000504277313130018300373003728287328767100102010000203000030130300371110021109101010000100640216222963010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037241006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300375110021109101010000100640216232963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  udot v0.4s, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233001032954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003723300612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037233033612953925101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003723300612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003723200612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003723300612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003723300612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003723200612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003723300612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003723300612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003723310000061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000006403162229630010000103003830038300383003830038
100243003723200040061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037233000042061295482510010121000012100005042773130300223003730037282873287671001220100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003723300000061295482510012121000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003723300000061295482510010101000010100005042773130300183003730037282873287671001220100002030000300373003711100211091010100001000006424162229632210000103003830038300383003830038
100243003723300000061295482510012121000012100006042773130300183003730037282873287671001220100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037232000312061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000606402162229630210000103003830038300383003830038
100243003723300000061295482510012121000010100006042773130300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037233000030117295482510012121000012100006042773130300183003730037282873287671001020100002030000300373003711100211091010100001000006423163429632210000103003830038300383003830038
1002430037233000000722295482510012121000012100006042773130300183003730037282873287671001220100002030000300373003711100211091010100001000006422162229630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  udot v0.4s, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acl1d tlb miss nonspec (c1)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723200612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
1020430037233001032954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003723200892954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
1020430037233012612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
1020430037232101032954825101001001000010010000500427731303001830086300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
10204300372320061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000141171000161129634100001003003830038300383003830038
102043003723300612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
10204300372330061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000153071001161129634100001003003830038300383003830038
102043003723300612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383008130038
102043003723200612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372320000061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372320000061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372330000061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037233000007262954825100101010000101000050427731330018300373008428287262876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372320000061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372330000061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372320000061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372320000061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003723301000251295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372320000061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  udot v0.4s, v8.16b, v9.16b
  movi v1.16b, 0
  udot v1.4s, v8.16b, v9.16b
  movi v2.16b, 0
  udot v2.4s, v8.16b, v9.16b
  movi v3.16b, 0
  udot v3.4s, v8.16b, v9.16b
  movi v4.16b, 0
  udot v4.4s, v8.16b, v9.16b
  movi v5.16b, 0
  udot v5.4s, v8.16b, v9.16b
  movi v6.16b, 0
  udot v6.4s, v8.16b, v9.16b
  movi v7.16b, 0
  udot v7.4s, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420065155000392580125125800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100000101150316332006101600001002006520363200652006520065
16020420064155010392580100100800001008000050664000000200452006420064322801002008000020024000020064200641116020110099100100160000100000101140416442006101600001002006520065200652006520065
16020420064155000392580100100800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100000101150616542006101600001002006520065200652006520065
16020420064155000392580100100800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100190101130316442006101600001002006520065200652006520065
16020420064155000392580100100800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100000101140416562006101600001002006520065200652006520065
16020420064156000392580100100800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100100101150316442006101600001002006520065200652006520065
16020420064156000392580100100800001008000050064000000200452006420064322801002008000020224000020064200641116020110099100100160000100001101130416532006101600001002006520065200652006520065
16020420064155000392580100100800001008000050064000010200452006420064322801002008000020024000020064200641116020110099100100160000100000101140416532006101600001002006520065200652006520065
16020420064156000392580100100800001008000050064000010200452006420064322801002008000020024000020064200641116020110099100100160000100930101150416442006101600001002006520065200652006520065
16020420064155000392580100100800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100000101150516542006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242009215500000000512580012128000012800006264000011200272004620046322800122080000202400002005020050111600211091010160000100000030010033622102442284200472300160000102005120051200512005120051
160024200461550000001204525800121280000128000062640000012003120046201363228001220800002024000020046200461116002110910101600001000000300100333111024221510200432150160000102004720051200472005120047
160024200461561000000051258001212800001280000626400000120027200502004632280012208000020240000200462004611160021109101016000010000003001003031292041148200512160160000102005120047200472005120047
160024200461550000000045258001212800001280000626400001120027200462004632280012208000020240000200462004611160021109101016000010000001050010030311424211104202462310160000102004720051200472005120047
160024200461550000000051258001212800001280000626400000120027200462005032280012208000020240000200462004711160021109101016000010000000001003031182021174200432150160000102004720047200472004720047
1600242004615500000000452580012128000012800006264000011200312004620046322800122080000202400002004720046111600211091010160000100000000010034622420221114200432150160000102004720047200472004720047
160024200461550000000045258001212800001280000626400001120031200462004632280012208000020240000200462004611160021109101016000010000009001003031142421247200432150160000102005120051200512004720051
1600242004615610000000452580012128000012800006264000001200312005020050322800122080000202400002004620046111600211091010160000100000012001002762272021147200432150160000102005120051200512004720051
1600242004615510000000932580012128000012800006264000001200272004620050322800122080000202400002004620046111600211091010160000100000090010027311720211511200432150160000102004720047200472004720047
160024200461560000000045258001212800001280000626400001120031200502004632280012208000020240000200462004611160021109101016000010000009001003331242441248200472150160000102004720047200512004720052

Test 6: throughput

Count: 16

Code:

  udot v0.4s, v16.16b, v17.16b
  udot v1.4s, v16.16b, v17.16b
  udot v2.4s, v16.16b, v17.16b
  udot v3.4s, v16.16b, v17.16b
  udot v4.4s, v16.16b, v17.16b
  udot v5.4s, v16.16b, v17.16b
  udot v6.4s, v16.16b, v17.16b
  udot v7.4s, v16.16b, v17.16b
  udot v8.4s, v16.16b, v17.16b
  udot v9.4s, v16.16b, v17.16b
  udot v10.4s, v16.16b, v17.16b
  udot v11.4s, v16.16b, v17.16b
  udot v12.4s, v16.16b, v17.16b
  udot v13.4s, v16.16b, v17.16b
  udot v14.4s, v16.16b, v17.16b
  udot v15.4s, v16.16b, v17.16b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f373a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440124310000000009225160101100160017100160000500128000040020040048400391997332000616010020016000020048000040039400391116020110099100100160000100000001210110216114003601600001004004040049400404004040040
1602044003931100000000412516011710016000010016000050012800004002904003940039199733199971601002001600002004800004003940039111602011009910010016000010000000010110116114003601600001004004940040400404004040049
16020440039310000000004212516011810016000010016000050012800004002004003940039199733199971601002001600002004800004004840048111602011009910010016000010000000010110116114003601600001004004040040400404004940049
1602044004831100000000412516010010016000010016000050023989994002904004840039199733199971601002001600002004800004004840048111602011009910010016000010000000010110116114004501600001004004040040400494004040049
160204400483110000000017092516011710016000010016000050012800004002904004840048199733200061601002001600002004800004003940039111602011009910010016000010000000010110116114004501600001004004040040400404004040040
160204400393100000001707062516010010016001710016000050012800004002904003940039199733199971601002001600002004800004004840039111602011009910010016000010000000010110116114003601600001004004940049400494004040041
1602044004831000000000922516010010016000010016000050023989994002004004840039199733199971601002001600002004800004003940039111602011009910010016000010000000010110116114003601600001004004040049400494004940041
1602044004831000000000412516010010016001710016000050013199994002004003940048199733199971601002001600002004800004003940048111602011009910010016000010000000010110116114004501600001004004040041400404004040040
16020440039310000012000412516010010016000010016000050012800004012004004840048199733200061601002001600002004800004004840039111602011009910010016000010000000010110116114003601600001004004940040400404004940040
160204400393110000001709402516011710016000010016000050012800004002904003940039199733199971601002001600002004800004003940048111602011009910010016000010000000010110116114003601600001004004040049400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)030918191e373a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440070311000900462516002810160000101600005012800000140020400484004819996320019160010201600002048000040039400391116002110910101600001000010022311171621117164003601550160000104004040040400404004040040
16002440039310000000552516001010160000101600005023989991140020400494003919996320029160010201600002048000040039400391116002110910101600001000010022311181622119204004501650160000104004040040400404004040040
16002440039310001000522516001010160000101600005012800001140020400394003919996320019160010201600002048000040039400391116002110910101600001000010022311191621112164003601550160000104004040040400404004040040
16002440039310000000462516001010160000101600005012800001140029400494003919996320019160010201600002048000040039400391116002110910101600001000010024311171622219194003601550160000104004040040400404004040040
160024400393100009005525160010101600001016000050128000011400204004840048199963200191600102016000020480000400394003911160021109101016000010000100223111916211191940036015100160000104004040040400404004040040
16002440039310000000462516001010160000101600005012800001140020400394003919996320029160010201600002048000040039400391116002110910101600001000010022311171641119174003603050160000104004940040400404004040040
160024400393110000006725160010101600001016000050239899911400214004940039199963200291600102016000020480000400394003911160021109101016000010000100223121516211171540046015100160000104004040040400504005040040
16002440039310010000462516001010160000101600005012800001140020400394003919996320019160010201600002048000040039400391116002110910101600001000010022622181621118174003601550160000104004040040400404004140040
160024400393100001200462516001010160000101600005012800001140020400394004919996320019160010201600002048000040039400391116002110910101600001000010022311171621113194003601560160000104004040040400404004040040
16002440039310000000472516001010160000101600005012800001140020400394003919996320019160010201600002048000040039400391116002110910101600001000010022311151621119134003601550160000104004940040400404004040049